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gulotta
Contributor
Contributor
11,364 Views
Registered: ‎06-05-2010

How to constrain skew between multiple routes

Is there any way to match delays between multiple routes in a Xilinx device?  This is a non-standard application where the launching registers are floorplanned next to each other in one corner, and likewise, the receiving registers in an opposite corner.   

 

MAXSKEW only works on a single driver.  MAXDELAY gaurantees a max but not a min.  A MINDELAY would be what we're after however it doesn't exist to my knowledge. 

 

Are there any undocumented UCF constraints, or will SDC constraints work (when available), or is there some obscure way to use DIRT strings or other tricks?

 

Thanks,

Mike

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15 Replies
eteam00
Instructor
Instructor
11,329 Views
Registered: ‎07-21-2009

There may be more than one way to approach this problem, depending on the specific requirements of the problem.

 

  • What clock(s) and frequency are you using for the registers?
  • What other global clocks are used in your design?
  • What is your target device (including speed grade)?

 

-- Bob Elkind

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gulotta
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Registered: ‎06-05-2010

This is a non-standard, proprietary application that requires a way to control routing skew.  It looks like SDC constraints have both max and min leading me to believe I can do it in Altera today, Xilinx tomorrow.  Is there anyway to accomplish this with UCF?  Any other ideas to accomplish this in Xilinx today?

 

Thanks,

Mike

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eteam00
Instructor
Instructor
11,323 Views
Registered: ‎07-21-2009

If this is too proprietary for public discussion, suggest you open a webcase for direct, confidential support.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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gulotta
Contributor
Contributor
11,320 Views
Registered: ‎06-05-2010

It's unclear why you would need to understand a customer's application when asked a precisely worded question such as this one.

 

Based on your response I presume Xilinx cannot support this.

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eteam00
Instructor
Instructor
11,311 Views
Registered: ‎07-21-2009

Based on your response I presume Xilinx cannot support this.

 

What a silly thing to say!

 

You have nothing to lose by giving the Xilinx webcase support folks a try, and they are much more likely to provide specific and useful help when you are free to describe the details of your design problem.

 

As I said before, there are usually several different solutions to a single problem, and you should not prematurely rule out any useful solution approaches.

 

Remember, this is a user forum, not first-line customer support.  There are Xilinx employees providing help, but in many cases this is not their primary job responsibility.  Most of the correspondents in these forums (including me) are unpaid volounteers who don't (usually) deserve gratuitous insults.  We prefer to earn our insults, whenever possible!

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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gulotta
Contributor
Contributor
11,308 Views
Registered: ‎06-05-2010

Bob,

I posted a question.  If you don't know the answer that's ok, just say so, or better yet let someone with advanced timing constraints experience reply with an answer.

 

 

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eteam00
Instructor
Instructor
11,303 Views
Registered: ‎07-21-2009

I posted a question.  If you don't know the answer that's ok, just say so, or better yet let someone with advanced timing constraints experience reply with an answer.

 

The webcase folks can -- and will -- direct to you someone with advanced timing constraints expertise.  For a problem such as yours, with such narrow and unusual scope, quick and useful response in the user forums is a hit-or-miss proposition, depending on who happens to be surfing the forums at the moment.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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austin
Scholar
Scholar
11,297 Views
Registered: ‎02-27-2008

g,

 

Using FPGA_Editor one can manually route to get identical resources which could get as close as is physically possible matched skews.

 

Presumably, constraints can be used to get close, and then examine them and fix them as defined above.


This sounds like an asynchronous design, which is completely unsupported, and discouraged.  If Altera supports it, go play those dangerous games with them (process variation will make this an ongoing support issue, which makes it unattractive to us -- waste of time and money for a dubious benefit).  Keeping Altera engaged in losing time and money is just fine with me.

 

If this is a synchronous design, then it is unclear why the delays must be matched.

 

If you can not explain why this is needed in this forum, then it becomes impossible to suggest solutions.  If we know more, they may be better and supportable solutions.

 

http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf

 

see page 80 for IO offset in before and after constraints (which do what you desire for IO pins)

 

also examine FROM:TO constraints to get a group of signals all set to a minimum

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
gulotta
Contributor
Contributor
11,292 Views
Registered: ‎06-05-2010

I thought someone on the forum might suggest and/or have experience with SDC constraints such as set_min_delay, set_max_delay, etc.  I think my answer is UCF does not support bus routing skew, where SDC may.  I opened a hotline case to get more insight into Xilinx's future support of SDC. 

 

 

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barriet
Xilinx Employee
Xilinx Employee
10,449 Views
Registered: ‎08-13-2007

Mike,

The way I've seen this done is:

-LOC the source (in this case, FFs)

-LOC the destination (also FFs here)

-manually route the nets (careful to avoid bank-shots, match traces as well as possible to limit PVT variation, etc.)

-use DiRT strings in the ucf (from FED)  to preserve the routes

-constrain the paths in the ucf so it will report the paths in the twr

 

Your success here likely depends on target device (family & die size), how well you need them matched, etc.

It is also effectively an unsupported flow... ;)

I don't believe there is any way to accomplish what you want with ucf.

You could try FROM/TO but I don't think it will do what you want.

 

Good luck.

 

bt

 

gulotta
Contributor
Contributor
10,437 Views
Registered: ‎06-05-2010

Thanks Barrie,

That's what I was looking for.  I'll see what the hotline comes up with regard to Xilinx's future support of SDCs.  For what it's worth, here's a contraint from Altera's doc that appears to do what we're looking for...

 

set_max_skew constraint is used to perform maximum allowable skew analysis between sets of registers or ports. In order to constrain skew across multiple paths, all such paths must be defined within a single set_max_skew constraint.

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mlaprade
Visitor
Visitor
10,383 Views
Registered: ‎02-08-2012

I have the same problem. I am trying to build a DRU (Data Recovery Unit). There are about 8 Xilinx app notes on how to do it. However they make use of LVDS inputs. As I only have single ended input, I can't do this. So I'm essentially building the same thing with internal flip flops. I understand that I can hand place the flops but it would be nice if there was a way to specify min AND max on the route. I have to sample the data  with 8 phases of the clock so I need the 8 routes to be very similar in length (within 200 ps).

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Anonymous
Not applicable
9,793 Views

I'm having an identical issue with a 7-series design using XDC constraints. I'm looking for a set_max_skew constraint that does the exact same thing the MAXSKEW constraint did in UCF constraints. I have one signal coming in that goes to 12 flops running off of 12 different phases of the capture clock. I need to ensure that the wire lengths from the input buffer to each of the 12 flops are as close to the same delay as possible. I successfully accomplished this in a Spartan 6 design using the MAXSKEW constraint but I can't duplicate this with XDC constraints. All 12 flops are physically placed as close together as possible but the wire delays from the input pad to each of the 12 flops  varies from as little as 600 ps to as much as 1.9 ns. I can't recover the proper phase if the input signal unless those 12 routes are very close in delay. My situation is similar to the data recovery application note that XIlinx published back in 2007. How do I duplicate the functionality of the MAXSKEW constraint in XDC notation? I've tried set_max_delay followed by set_min_delay but the last constraint overrides the previous one and I can long wires. I agred that Altera's set_max_delay constraint is the equivalent to Xilinx's MAXDELAY UCF constraint but I see no replacement for it in XDC notation. How are people doing this?

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romain.lefort
Contributor
Contributor
8,065 Views
Registered: ‎02-05-2013

Any update ?

Does any set_max_skew or equivalent command exist ?

 

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graces
Moderator
Moderator
8,056 Views
Registered: ‎07-16-2008

There's no plan to support set_max_skew command.

We already support set_data_check for setting skew requirement.

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