02-04-2009 10:19 PM
Some OFFSET constraints confused me...
Could someone help me...?
From the xilinx's white paper I found that only external clock could be used in OFFSET constraints.
But if I want to constraint some FF(clocked by DCM's output, maybe x2 x1/2 or some value) to some PAD(output port) delay as 5.3ns.
How do I constraint my "OFFSET out" for that PAD?
It doesn't make sense if I use clock input pad.
Because the clock's frequency of that FF is different from clock input pad.
I shouldn't use the clock input pad to check that path's timing...
If one output port's fanin cone comes from <i> input port (constrained by OFFSET IN) <ii> some FFs (constrained by PERIOD).
How do I constraint that output port to let ISE can analyze these two paths?
Does OFFSET OUT only cover FFs to PAD ? => I will lost paths : Input PAD to OUTput PAD.
Thank you very much!!!!
02-05-2009 07:17 PM
1. OFFSET OUT are usually used in System-Synchronous design, so the reference clock is the external clock on the Pad.
In your situation, I think you can force the output register into the IOB, this would get minimum output delay. Another method is use From TO constraint.
2. You also can analyze the PAD to PAD path by using FROM TO constraint.
02-17-2009 11:35 PM
What do you mean System-Synchronous?
Does it mean input data and the output data should be forced to IOB and be sampled by external clock on the pad ?
==> So we can set Offset in and out constraints in this situation?
And the reference clock of all registers inside FPGA except those in IOB should be driven by BUFG?
02-18-2009 01:28 AM
Generally, OFFSET OUT constraint is used to control the setup/hold requirement of the downstream devices. System-Synchronous means the clocks of FPGA and other device comes from a same source and have same phase. If the downstream device has an asynchronous clock, then the OFFSET OUT constraints has no meaning.
02-18-2009 07:39 PM
The clock path analysis for Offset IN/OUT constraints doesn't care for the frequency change. But it considers the phase.
You could see the Clock Arrival Time changes when the phase changes.
If both Clk0 and Clk2x (routed on the global network) drives the last level of register inside the FPGA before the data goes out of it, the clock path delay value could be similar.