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Observer
Observer
10,059 Views
Registered: ‎06-26-2014

How to constraint Si5324 clock

Hi all,

 

I have a question regarding a design which is creating timing violations on the ZC706 board.

I am using the Zynq PS7 IP to generate a 50MHz clock(FCLK_CLK0), converting it to differential clock inputs,and tying these to output pins(AE20 and AD20) which provide input to  , and use I2C programming to produce a 312.5MHz clock as the Si5324 jitter attenuated clock, which I source by typing my input pins to AC8 and AC7.

 

How would I represent the relationship between this 50MHz clock, and the 312.5 MHz clock- Are these to be treated asynchronous because there is no logical connect, but only phyical connect through the Si5324 chip ?

 

Is there anything I should specif in the constraints to show their relationship ?

 

Thanks

Sowmya

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Scholar
Scholar
10,048 Views
Registered: ‎02-27-2008

s,

 

Let me see if I understand this:  you create a 50 MHz clock, that gets used as an input to the board sythensizer, which in turn creates a 312.5 MHz clock.

 

As that is not a simplke integer relationship (times 25, divide by 4), there is no easilyusable phase relationship between these two clock domains.  So I would treat them as asynchronous for any signals crossing between them.  That will cause the need to use two stage (or three stage) synchronizers to prevent metastability, or the use of FIFO (BRAM) if sending/receiving data across them.

 

Worrying about how you might make use of the fact that the two clocks are related (25/4) just hurts my head, and I am not sure how you would be able to constrain the tools in any useful way because it is not a multi-cycle path (for example if it was 6X, going from 50 to 300, you could make a 5 cycle multi-cycle path.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
10,041 Views
Registered: ‎06-26-2014

Thanks Austin, If I am using an AXI Interconnect IP between the PS7 and the logic which is clocked by the Si5324, doesn't it account for the FIFO/synchronizers, do I still need to create them explicitly?

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Scholar
Scholar
10,029 Views
Registered: ‎02-27-2008

I will let someone who knows more than I reply to that,


As far as I know, AXI uses the PS clock for the HP, GP, or ACP bus in the processor side, so to make it work I beleive you must use that clock as passed through to the programmable logic side.

 

Look at ug761

 

AXI Reference Guide - Xilinx

www.xilinx.com/.../ip.../axi.../ug761_axi_reference_guide.pdf
Xilinx
Jan 18, 2012 - Added limitation related to CORE Generator use in AXI Interconnect Core .... AXI is part of ARM AMBA, a family of micro controller buses first ..... Generates REGION outputs for use by slave devices with multiple address decode ... Asynchronous clock conversion (uses more storage and incurs more latency ...
 
Which seems to imply that if you tell it the domains are asynchronous, it adds the required logic (synchronizers, and probably a FIFO/BRAM?).
Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer
Observer
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Registered: ‎06-26-2014

I have not been succesful configuring the AXI interconnect with asynchronous clocks,Can someone help me with the settings to make it asynchronous ? I couldn't find any, and merely connecting them continues to give the critical warning:

 

"CRITICAL WARNING: [BD 41-1363] The clock pins '/axi_interconnect_0/M00_ACLK' (interface '/axi_interconnect_0/M00_AXI') and '/axi_gpio_0/s_axi_aclk' (interface '/axi_gpio_0/S_AXI') must be connected to the same source "

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