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16,323 Views
Registered: ‎11-03-2013

How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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Hey guys! In my design I am using a  DCM_ADV using core generator. I have no phase/frequency relation between input(CLKIN) and output(CLKFX). I am using DCM Frequency Synthesizer, as I have to generate a 40MHz from the builton 32MHz oscillator(Virtex-5 xc5vfx100t-1ff1136). As I am in no need of any feedback I unchecked the CLK0 pin and checked only CLKFX and LOCKED pins. I just want to give that 40MHz  from CLKFX to my INIT_CLK port of aurora module.

And I gave options as: input clock freq: 32MHz, CLKIN source: external(single), feedback source=none. This is my 1st time using a DCM. So, after writing the UCF, everything is fine, I removed my cross clock domain constraints from the UCF, but during implementation I  am getting the following warning::::::

The Clock Modifying COMP, Inst_clkgen_40MHz/DCM_ADV_INST, has the attribute CLK_FEEDBACK set to NONE.
   No phase relationship exists between the input and output clocks of this Clock Modifying COMP. Data paths between
   these clock domains must be constrained using FROM/TO constraints.

So, I came to know, how to write this constraint, but I am confused what to write in place of maximum delay of data paths. What is that?

Thaniks,

jeevanreddymandali
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Instructor
Instructor
25,933 Views
Registered: ‎08-14-2007

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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On page 19 you can see that the example shows two clocks each of which clock at least one (only one shown) flip-flop.  If there are no flops clocked, then there are no paths of type "Data_A_B" to constrain.  Also be aware that the FROM TO constraint is unidirectional.  So if you have paths going between the two timing groups in both directions you'd need two such constraints.  In any case you don't really have two timing domains.  i.e. you can treat the output of the DCM as if it were an on-board 40 MHz oscillator.  And you should definitely ignore the original warning.  If the fact that you have no synchronous elements in one of the clock domains doesn't suppress it, I don't see any way to end up with no warnings.

-- Gabor
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Instructor
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Registered: ‎08-14-2007

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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The tools are telling you that they regard your 32 MHz and 40 MHz clocks as unrelated and will not analyze timing on cross-clock-domain paths.  If your design also treats the clocks as unrelated, i.e. you properly synchronize signals crossing the domains and don't depend on any particular phase relation betweeen the two, then you don't need to do anything.  Sometimes it's a good idea to add FROM : TO constraints if you want to constrain worst case timing.  This might be true if you have multiple signals crossing domains as a group and want to ensure that they arrive within +/- 1 clock cycle of eachother (sorry, you can't make that zero).  Then you should add a constraint between the two timing groups (defined using TNM_NET for each clock source) with a delay value less than or equal to the period of the destination clock and the keyword "DATAPATHONLY" to prevent hold time checks on these paths.

-- Gabor
16,311 Views
Registered: ‎11-03-2013

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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So, if there is no particular phase relation betweeen the two, input clock & output clock, then I need not do anything? I can ignore this warning right? Okay, thanks UCF is fairly new to me! I by following the warning wrote the following lines and got 3 warnings X-(.

What i did was: this is my DCM port mapping:

Inst_clkgen_40MHz: clkgen_40MHz PORT MAP(
		CLKIN_IN => F_CLK_32MHz,
		RST_IN => '0',
		CLKFX_OUT => clk_40mhz,
		CLKIN_IBUFG_OUT => open,
		LOCKED_OUT => open
	);

 So, I wrote like:

NET "F_CLK_32MHz" TNM_NET = FFS "GRP_A";
NET "clk_40mhz" TNM_NET = FFS "GRP_B";
TIMESPEC TS_TOINITCLK = FROM "GRP_A" TO "GRP_B" 25 ns DATAPATHONLY;

 

I wrote this following timing_constraints_ug.pdf!

And the warnigs are:

 

1) GRP_A was distributed to a DCM but new TNM constraints were not derived. The requirement for derived TNM constraints is that the distributed TNM is referenced by no more than a single PERIOD constraint. Non-PERIOD referencers are also not allowed. This TNM is used in the following user groups or specifications:
   <TIMESPEC TS_TOINITCLK = FROM "GRP_A" TO "GRP_B" 25 ns DATAPATHONLY;>[aurora_8b10b_v6_1_example_design.ucf(81)]

 

2)The TNM 'GRP_A', does not directly or indirectly drive any flip-flops, latches and/or RAMs and cannot be actively used by the referencing MaxDelay constraint 'TS_TOINITCLK'. If clock manager blocks are directly or indirectly driven, a new TNM constraint will not be derived since the referencing constraint is not a PERIOD constraint. This TNM is used in the following user group or specification:
   <TIMESPEC TS_TOINITCLK = FROM "GRP_A" TO "GRP_B" 25 ns DATAPATHONLY;>
   [aurora_8b10b_v6_1_example_design.ucf(81)]

 

3)The following specification is invalid because the referenced TNM constraint was removed:
   <TIMESPEC TS_TOINITCLK = FROM "GRP_A" TO "GRP_B" 25 ns DATAPATHONLY;>
   [aurora_8b10b_v6_1_example_design.ucf(81)]

 

Correct me please! And hey thanks for making your time!

Regards,

jeevanreddymandali
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Instructor
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Registered: ‎08-14-2007

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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What errors did you get?  It looks OK to me, but that depends on whether the net names in your code match those in the synthesized (translated) design.  Also note that the FFS keyword only associates with fabric flops and not other synchronous elements like BRAM, SRL, DSP48, etc.  Normally you don't want to use this unless you're sure you don't want to apply the constraint to those other element types.

-- Gabor
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Instructor
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Registered: ‎08-14-2007

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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Sorry, I posted before you edited the last post.

 

It looks like you have no synchronous elements clocked on the 32 MHz input clock.  Is this true?  If so the original warning was entirely bogus, since there are no paths to which to apply the FROM TO constraint.  Note that bogus warnings are not unusual, and it is often counterproductive to try to remove all warnings rather than just learning which ones you can ignore.

-- Gabor
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16,302 Views
Registered: ‎11-03-2013

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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Hey there are these warnings. What should i do about them? And yes net names match. But why am I getting these warnings?
jeevanreddymandali
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Registered: ‎11-03-2013

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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Hey its totally okay Gabor! Wow thanks and yes I donot have any synchronous elements on input clock. I just wanted the 40MHz output, thats it. So, I will ignore them for now! But friend one thing, I wrote ucf reading the official timing_constraint_ug.pdf(page 19) under Asynchronous Clock Domains concept. So, please have a look at it. I attached the pdf.
Thanks,

jeevanreddymandali
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Instructor
Instructor
25,934 Views
Registered: ‎08-14-2007

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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On page 19 you can see that the example shows two clocks each of which clock at least one (only one shown) flip-flop.  If there are no flops clocked, then there are no paths of type "Data_A_B" to constrain.  Also be aware that the FROM TO constraint is unidirectional.  So if you have paths going between the two timing groups in both directions you'd need two such constraints.  In any case you don't really have two timing domains.  i.e. you can treat the output of the DCM as if it were an on-board 40 MHz oscillator.  And you should definitely ignore the original warning.  If the fact that you have no synchronous elements in one of the clock domains doesn't suppress it, I don't see any way to end up with no warnings.

-- Gabor
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16,289 Views
Registered: ‎11-03-2013

Re: How to define the maximum delay of the data paths using the FROM-TO constraint between the two time groups

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Thanks a lot!
Regards,
Best of luck,
jeevanreddymandali
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