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Explorer
Explorer
1,048 Views
Registered: ‎02-13-2019

How to ged rid of the Negative Slack

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Hi, I'm Jose and I'm a bit new in the area of Timing Analysis.
I have the next situation. I am with a design but I have a problem of timing (Negative Slack) in the circuit I've tried to solve the problem adding D-flip-flop between the modules which the problem was reported with in the Timing Summary. The thing is that I added the registers but the negative slack doesn´t dissapear completely (though it was reduced considerately) instead remain in other places.

 

The remaining  endpoints with problems are 4, as show the Fig.1 and Fig.2

T2.JPG

Fig.1. Number of failing endpoints:4.

T1.JPG

Fig.2. Paths with timing.

The thing is that when I select the schematic of the first failed endpoint as shown in Fig.3 I notice something strange. First, it is supposed that the module register5 (a D-FlipFlop) and the module intCounterAndConcatADC share a data bus of 4 bits, and I don´t know why appears 30:0. Second, the dataToFIFO[92] and count_reg[4] appear within register5 but really belong to the module intCounterAndConcatADC, why?

last, How can I get rid of that negative slack? I probed to add another register after register5 but the timing negative slack got increased.

 

T3.JPG

Fig.3. Path with timing,eschematic

 

 

Thank you

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Xilinx Employee
Xilinx Employee
1,036 Views
Registered: ‎05-22-2018

Re: How to ged rid of the Negative Slack

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Hi @jose09621 ,

Please follow the below steps and check whether it helps:

route_design -unroute

place_design -unplace

place_design -directive Explore

physopt_design -directive Explore

route_design -directive Explore

And then report_timing_summary.

Thanks,

Raj

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Xilinx Employee
Xilinx Employee
1,037 Views
Registered: ‎05-22-2018

Re: How to ged rid of the Negative Slack

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Hi @jose09621 ,

Please follow the below steps and check whether it helps:

route_design -unroute

place_design -unplace

place_design -directive Explore

physopt_design -directive Explore

route_design -directive Explore

And then report_timing_summary.

Thanks,

Raj

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Moderator
Moderator
1,019 Views
Registered: ‎11-04-2010

Re: How to ged rid of the Negative Slack

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Hi , @jose09621 ,

The WNS and TNS is not large in this design and trying some different place_design directives can achieve timing with high probability.

For the D[30:0] bus, please check what the other logic connected on it. 

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t5.png
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Explorer
Explorer
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Registered: ‎02-13-2019

Re: How to ged rid of the Negative Slack

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thank you @hongh  and @rshekhaw  for answer.

 

@rshekhaw rshekhaw , the method you say implies that I have to do it every time I implement that project? for example if I join it to another bigger project I need to do the same? is there a permanent solution?

@hongh  , what are the directives you are saying? in the same way, does it implies that I have to do it every time I implement that project?

thanks

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Moderator
Moderator
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Registered: ‎11-04-2010

Re: How to ged rid of the Negative Slack

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Hi, @jose09621 ,

For Example, the place_design directives you can try:  Explore/ExtraNetDelay_high/ExtraNetDelay_low...

phys_opt_design can also be added after place_design and route_design.

For the detailed information, you can refer to UG904.

It's just the effort to archive timing closure with tool's options, and you can continue to optimize your design, Ex: reduce the logic level of the critical path... 

With the further optimization of the design, maybe you don't need to try so many directives next time.

 

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Visitor
Visitor
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Registered: ‎04-08-2018

Re: How to ged rid of the Negative Slack

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The negative slack is pretty small and normally the tool can resolve them. Logic level is resonable but fanout is a little high. Register replication may help.

What is the clock frequency? and CLB utilization?

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc
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Explorer
Explorer
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Registered: ‎02-13-2019

Re: How to ged rid of the Negative Slack

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@hongh   thank you for tell me what the common directives are and to specify the User Guide that is related with these about.

@rshekhaw , your commands worked deleting the timing problem. what more do you recommend to make the solution permanent?


@peterk  the frequency is 500 MHz. What is a Register application? to segment the circuit? I don´t know where to see the CLB utilization you are talking about. I searched but I didn't find some ilustrating proccess to do it. How do I see it?

 

thank you for the help

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Visitor
Visitor
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Registered: ‎04-08-2018

Re: How to ged rid of the Negative Slack

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500 MHz is pretty fast. Since using explore directive works, I would just keep using that.

Register replication is duplicating registers when fanout is greater than the set amount (the default maybe 10,000). You can do this manually in your code or set it in the synthesis options. Becareful setting the option since this applies to the whole design. I think the latest Vivado allows synthesis strategy apply to block level.

report_utilization will show CLB (LUTs) used in your design.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc
Explorer
Explorer
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Registered: ‎02-13-2019

Re: How to ged rid of the Negative Slack

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Hi @peterk 

This is the report

 

LUT.JPG

 

thank you.

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