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Visitor
Visitor
7,353 Views
Registered: ‎01-19-2009

How to reduce Offset Out

Hi, every one.

 

Currently, I am designing some H/W working on 200MHz using S3A.

But I have a problem. I can't reduce Offset Out although I insert DFF between Logic and IOB.

 

Offset out must be lower than 5ns.

By the way, it is around 9ns.

 

Please let me know your Know-How.

 

 

 

 

 

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3 Replies
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Participant
Participant
7,273 Views
Registered: ‎05-12-2008

Re: How to reduce Offset Out

Hello,

Maybe you can use a DCM to do a phase shift on the clock.

 

Regards,

Jared

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Xilinx Employee
Xilinx Employee
7,154 Views
Registered: ‎07-30-2007

Re: How to reduce Offset Out

Also make sure that the FF is actually packed into the IOB.  The timing report will tell you which parts of the path are too long- you'll then have to address the biggest delay offenders.  For example, you'll want to check if most of the delay is in the data path or in the clock path, and proceed from there...
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Anonymous
Not applicable
7,141 Views

Re: How to reduce Offset Out

Adding one addtional level of register, and pack it into the IOB will be the easiest way, if you won't make any changes to the clock routing.
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