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Voyager
Voyager
233 Views
Registered: ‎10-12-2016

How to reduce the paths delay inside a module ?

HI Friends, 

I am getting too much timing violations on intra clocks paths. i did Floor plan and that reduced a lot of timing violations. but still i have 92 failing paths. 

Timing.PNG

-Sampath
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1 Reply
Xilinx Employee
Xilinx Employee
223 Views
Registered: ‎05-22-2018

Re: How to reduce the paths delay inside a module ?

Hi @ssampath ,

As in Timing tab the level is in paths is of 9 and 10, to reduce logic levels check this AR link, might be helpful:

https://www.xilinx.com/support/answers/9417.html

Thanks,

Raj

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