08-11-2018 07:01 AM - edited 08-11-2018 07:12 AM
The design is described above. I have create master clock named as "mst_clk", what should i do to guarantee DFFs timing analysis. my constraint as below:
create_clock -name mst_ck -period xxx ...
create_generated_clock -name bck1_pre -source mst_ck [get_pins mux2_pre1.O] -divide 2 ...
create_generated_clock -name bck2_pre -source mst_ck [get_pins mux2_pre2.O] -divide 2 ...
create_generated_clock -name bck1_0 -source bck1_pre [get_pins bck1] -divide 1 -add -master_clock bck1_pre...
create_generated_clock -name bck1_1 -source bck2_pre [get_pins bck1] -divide 1 -add -master_clock bck2_pre...
set_clock_group -phyically_exclusive -group bck1_0 -group bck1_1
create_generated_clock -name bck2_0 -source bck1_pre [get_pins bck2] -divide 1 -add -master_clock bck1_pre...
create_generated_clock -name bck2_1 -source bck2_pre [get_pins bck2] -divide 1 -add -master_clock bck2_pre...
set_clock_group -phyically_exclusive -group bck2_0 -group bck2_1
set_case_analysis 0 [get_pins mux2_pre1.S]
set_case_analysis 0 [get_pins mux1_pre1.S]
above constraints are right? it seems that there are some problems from vivado timing result log
08-11-2018 07:55 AM
08-11-2018 04:43 PM
Before we talk about constraints, we need to know more about what you are trying to do.
From what I can see here, there is only one clock - mst_ck. This clock goes through a number of different paths, which ultimately end up either being mst_ck or mst_ck/2. So I don't understand why there are so many MUXes in your system.
Next, how are the different "operations" done:
- how is the /2 done? with flip-flops, with BUFGCE, with an MMCM/PLL?
- what does the /1 do? A divide by 1 doesn't do anything
- how are the MUXes implemented - RTL muxes or the BUFGMUX
In FPGAs there are a variety of dedicated clocking resources - clock capable pins, clock buffers (which can do division, multiplexing and gating), clock management cells (MMCMs and PLLs) and dedicated clock nets. Furthermore, there are limited combinations of these that keep things on "dedicated" resources and (more importantly) skew controlled and balanced. While powerful, these resources are pretty restrictive compared to the unrestricted capabilities of the clock tree building capabilities of ASICs.
Clock structures like the one you show here cannot be implemented in the dedicated FPGA clocking logic, and hence are very strongly discouraged. The characteristics of the clocks will be highly process/voltage/temperature dependent, not compensated and in some cases are even implementation dependent (they will change from run to run). As a result, the relationships of the clocks with each other and with the input clocks will vary and/or will have very large skews.
So, before you worry about constraining this thing, you need to make sure that it is viable in your design. Ideally, you should redesign it to simplify it and to target it to dedicated FPGA clocking resources. After that is done, we can talk about what needs specific constraints.
08-12-2018 06:52 AM
in above timing path A: launch clock's start point is mst_pre, but latch clock's start point is mst_ck from vivado timing report
timing path B: it appears that there is no timing path between slv_mux16to1.O and mst_pre
PS: the mean of red triangles is my generated clock setting point
08-12-2018 07:06 AM - edited 08-12-2018 07:07 AM
1. it's necessary there are so many MUXes in my system
2. div2 module means /2 /4 /8 ... /4096.. , in here just an example.
3. div1 means xor, special combinational logic.
4. as we know that v7 can use at most 32 bugs, but in my design, there are so many similar module, so we can't use bufgmux as mux2
5. in my design mux2 is replaced as glitch free clock mux.
so still need u to help me set valid timing constraints in my design. thanks~