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Observer sstadler
Observer
2,126 Views
Registered: ‎03-23-2016

How to set output delay for LTC2000A-11 DAC

I am trying to properly set up the set_output_delay for a source synchronous output from the FPGA to the LTC2000A DAC.  I have 2 DACs so there is DAC1 and DAC2.

 

I am using a select_io_wizard to set up the output for each DAC.

 

Here is the datasheet for the LTC2000A-11 DAC  http://cds.linear.com/docs/en/datasheet/2000afb.pdf 

On page 19 is the timing diagram, where I have set up the DAC to operate as in Figure 2. (DCKI_Q = 0, DCK_TADJ = 000)

From the timing table on page 8, for t11 and t12, setup time t11 = 570, and hold time t12 is -170. 

 

Because the hold time specified in the LTC2000A datasheet is negative, it looks like the data can be released before the clock edge?

 

My timing errors ballooned when I added this set of constraints.

 

Am I doing this correctly?

Would it be better to just put in zero or a small positive value for the hold time?  I'm sure the DAC would not mind if the data was held longer than specified?

 

I am using a Virtex 7 at 375MHz, xc7vx485tffg1761-2 (active)

 

I have the following in my constraints file (from the source synchronous output delay template in Vivado):

 

#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's Clocks - SRS 1 - 17 - 2018
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_generated_clock -name Po_DAC1_DATCLKIN_P_obj -source [get_pins FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/C] -divide_by 1 [get_ports Po_DAC1_DATCLKIN_P]
create_generated_clock -name Po_DAC2_DATCLKIN_P_obj -source [get_pins FSA_Main_i/DAC2_LTC2000_0/U0/LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/C] -divide_by 1 [get_ports Po_DAC2_DATCLKIN_P]

 

#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's set_output_delay's - SRS 1 - 17 - 2018
#-------------------------------------------------------------------------------------------------------------------------------------------------------
# Double Data Rate Source Synchronous Outputs
#
# Source synchronous output interfaces can be constrained either by the max data skew
# relative to the generated clock or by the destination device setup/hold requirements.
#
# Setup/Hold Case:
# Setup and hold requirements for the destination device and board trace delays are known.
#
# forwarded _________________________________
# clock __________| |______________
# | |
# tsu_r | thd_r tsu_f | thd_f
# <------>|<-------> <------>|<----->
# ________|_________ ________|_______
# data @ destination XXX__________________XXXXXXXXXXXXXXXX________________XXXXX
#
# Example of creating generated clock at clock output port
# create_generated_clock -name <gen_clock_name> -multiply_by 1 -source [get_pins <source_pin>] [get_ports <output_clock_port>]
# gen_clock_name is the name of forwarded clock here. It should be used below for defining "fwclk".

 

set fwclk_DAC1 Po_DAC1_DATCLKIN_P_obj; # forwarded clock name (generated using create_generated_clock at output clock port)
set fwclk_DAC2 Po_DAC2_DATCLKIN_P_obj; # forwarded clock name (generated using create_generated_clock at output clock port)
set tsu_r 0.570; # destination device setup time requirement for rising edge (0.570)
set thd_r -0.170; # destination device hold time requirement for rising edge (-0.170)
set tsu_f 0.570; # destination device setup time requirement for falling edge (0.570)
set thd_f -0.170; # destination device hold time requirement for falling edge (-0.170)
set trce_dly_max 0.000; # maximum board trace delay
set trce_dly_min 0.000; # minimum board trace delay
set output_port_DAC1 {PVo_DAC1_DA_P PVo_DAC1_DB_P}; # list of output ports
set output_port_DAC2 {PVo_DAC2_DA_P PVo_DAC2_DB_P}; # list of output ports

# Output Delay Constraints
set_output_delay -clock $fwclk_DAC1 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC1];
set_output_delay -clock $fwclk_DAC1 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC1];
set_output_delay -clock $fwclk_DAC1 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC1] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC1 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC1] -clock_fall -add_delay;

set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;

# Report Timing Template
# report_timing -rise_to [get_ports $output_ports] -max_paths 20 -nworst 2 -delay_type min_max -name src_sync_ddr_out_rise -file src_sync_ddr_out_rise.txt;
# report_timing -fall_to [get_ports $output_ports] -max_paths 20 -nworst 2 -delay_type min_max -name src_sync_ddr_out_fall -file src_sync_ddr_out_fall.txt;

 

Thank You,

Steve

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


.

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16 Replies
Historian
Historian
2,107 Views
Registered: ‎01-23-2009

Re: How to set output delay for LTC2000A-11 DAC

I don't see anything obviously wrong with the constraints (although I am not sure you told us what clock speed the forwarded clock is running at).

 

To see what is going on we need to see the complete detailed timing report for both the setup and hold check on at least one of the forwarded outputs.

 

Avrum

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Observer sstadler
Observer
2,090 Views
Registered: ‎03-23-2016

Re: How to set output delay for LTC2000A-11 DAC

Thank You for looking at this.

I am trying to get all of my inputs / outputs properly constrained for timing closure.

The DACs work with no set_output_delay constraints for those outputs, so I want to learn how to set this up properly, without breaking the functionality.

I un-commented out these constraints, and I am building the project again.

How would you like me to provide the detailed timing report for one of the forwarded outputs?  I can bring up the information to look at it, but there seems to be several different ways to get the information out of Vivado, so if you can guide me with the best steps for this, that would help me put the information in this post.

Thank You Again!

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


.

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Historian
Historian
2,083 Views
Registered: ‎01-23-2009

Re: How to set output delay for LTC2000A-11 DAC

Either screen shots of the detailed path reports from the GUI or the text output of the report timing command is fine

 

report_timing -setup -to [get_ports PVo_DAC1_DA_P]

report_timing  -hold -to [get_ports PVo_DAC1_DA_P]

 

Should be sufficient.

 

Avrum

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Observer sstadler
Observer
2,076 Views
Registered: ‎03-23-2016

Re: How to set output delay for LTC2000A-11 DAC

The forwarded clock is running at 375MHz.

There are no setup timing errors for these signals, only hold timing errors.

All of the DAC1 DataA and DataB signals and DAC2 DataA and DataB signals have hold timing -slack

Here is the timing report you requested,

 

I can program the TADJ in the LTC2000 chip if needed, or add tap delays in the selectio_wizard if needed, but since the signals coming out of the DACs are working without the set_output_delay constraints added, I was thinking I should not need to do that? (I have not yet tested if the DACs are working using the build with these set_output_delay constraints added)

 

Thank You!

 

report_timing -hold -to [get_ports PVo_DAC1_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date : Fri Feb 9 14:28:27 2018
| Host : SV2104 running 64-bit Service Pack 1 (build 7601)
| Command : report_timing -hold -to [get_ports PVo_DAC1_DA_P]
| Design : FSA_Main_wrapper
| Device : 7vx485t-ffg1761
| Speed File : -2 PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) : -0.168ns (arrival time - required time)
Source: FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/C
(rising edge-triggered cell ODDR clocked by CLK_375M_OBJ {rise@0.000ns fall@1.334ns period=2.667ns})
Destination: PVo_DAC1_DA_P[0]
(output port clocked by Po_DAC1_DATCLKIN_P_obj {rise@0.000ns fall@1.334ns period=2.667ns})
Path Group: Po_DAC1_DATCLKIN_P_obj
Path Type: Min at Fast Process Corner
Requirement: 0.000ns (Po_DAC1_DATCLKIN_P_obj rise@0.000ns - CLK_375M_OBJ rise@0.000ns)
Data Path Delay: 0.809ns (logic 0.809ns (100.000%) route 0.000ns (0.000%))
Logic Levels: 1 (OBUFDS=1)
Output Delay: 0.170ns
Clock Path Skew: 0.999ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.530ns
Source Clock Delay (SCD): 0.457ns
Clock Pessimism Removal (CPR): 0.074ns
Clock Uncertainty: 0.148ns ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.027ns
Discrete Jitter (DJ): 0.080ns
Phase Error (PE): 0.093ns

Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock CLK_375M_OBJ rise edge)
0.000 0.000 r
BUFR_X1Y9 BUFR 0.000 0.000 r FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
net (fo=55, routed) 0.255 0.255 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.447 -1.192 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.759 -0.433 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.026 -0.407 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
net (fo=3, routed) 0.035 -0.372 FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.026 -0.346 r FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
net (fo=164918, routed) 0.803 0.457 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
OLOGIC_X0Y8 ODDR r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/C
------------------------------------------------------------------- -------------------
OLOGIC_X0Y8 ODDR (Prop_oddr_C_Q) 0.192 0.649 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/Q
net (fo=1, routed) 0.000 0.649 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/data_out_to_pins_int[0]
AN30 OBUFDS (Prop_obufds_I_O) 0.617 1.266 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].obufds_inst/O
net (fo=0) 0.000 1.266 PVo_DAC1_DA_P[0]
AN30 r PVo_DAC1_DA_P[0] (OUT)
------------------------------------------------------------------- -------------------

(clock Po_DAC1_DATCLKIN_P_obj rise edge)
0.000 0.000 r
BUFR_X1Y9 BUFR 0.000 0.000 r FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
net (fo=55, routed) 0.298 0.298 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
-1.745 -1.447 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
net (fo=1, routed) 0.823 -0.624 FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
BUFGCTRL_X0Y1 BUFG (Prop_bufg_I_O) 0.030 -0.594 r FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
net (fo=3, routed) 0.039 -0.555 FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
BUFGCTRL_X0Y0 BUFGCTRL (Prop_bufgctrl_I0_O)
0.030 -0.525 r FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
net (fo=164918, routed) 1.064 0.539 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
OLOGIC_X0Y30 ODDR (Prop_oddr_C_Q) 0.221 0.760 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/Q
net (fo=1, routed) 0.000 0.760 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_fwd_out
AR34 OBUFDS (Prop_obufds_I_O) 0.770 1.530 r FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/obufds_inst/O
net (fo=0) 0.000 1.530 Po_DAC1_DATCLKIN_P
AR34 r Po_DAC1_DATCLKIN_P (OUT)
clock pessimism -0.074 1.456
clock uncertainty 0.148 1.604
output delay -0.170 1.434
-------------------------------------------------------------------
required time -1.434
arrival time 1.266
-------------------------------------------------------------------
slack -0.168

 

 

 

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


.

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Historian
Historian
2,073 Views
Registered: ‎01-23-2009

Re: How to set output delay for LTC2000A-11 DAC

Please paste them in a code box (the littke {i} symbol above the place to type) - the word wrap of the forum interface makes this very hard to follow.

 

Even though there is no setup violation, please show me the setup path as well.

 

Also, if you have changed your constraints, please attach a new version - it seems that the clock name in the report doesn't match your constraints...

 

Thanks,

 

Avrum

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Observer sstadler
Observer
2,063 Views
Registered: ‎03-23-2016

Re: How to set output delay for LTC2000A-11 DAC

 

The 375MHz clock comes from a high speed ADC, which goes to a MMCM to generate the FPGA system 375MHz clock, where clk_in1 of the clk_wiz_inst is the output of the selectio_wiz input IP that forwards the clock coming from the high speed ADC. 

The 375MHz system clock clocks the selectio_wizard output IP for the DACs.  

The CLK_375M_OBJ is the source clock for the forwarded clock.

The create_clock and create_generated_clock statements are following the timing reports.

 

 

 

 

report_timing  -hold -to [get_ports PVo_DAC1_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date         : Fri Feb  9 14:28:27 2018
| Host         : SV2104 running 64-bit Service Pack 1  (build 7601)
| Command      : report_timing -hold -to [get_ports PVo_DAC1_DA_P]
| Design       : FSA_Main_wrapper
| Device       : 7vx485t-ffg1761
| Speed File   : -2  PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (VIOLATED) :        -0.168ns  (arrival time - required time)
  Source:                 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/C
                            (rising edge-triggered cell ODDR clocked by CLK_375M_OBJ  {rise@0.000ns fall@1.334ns period=2.667ns})
  Destination:            PVo_DAC1_DA_P[0]
                            (output port clocked by Po_DAC1_DATCLKIN_P_obj  {rise@0.000ns fall@1.334ns period=2.667ns})
  Path Group:             Po_DAC1_DATCLKIN_P_obj
  Path Type:              Min at Fast Process Corner
  Requirement:            0.000ns  (Po_DAC1_DATCLKIN_P_obj rise@0.000ns - CLK_375M_OBJ rise@0.000ns)
  Data Path Delay:        0.809ns  (logic 0.809ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUFDS=1)
  Output Delay:           0.170ns
  Clock Path Skew:        0.999ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.530ns
    Source Clock Delay      (SCD):    0.457ns
    Clock Pessimism Removal (CPR):    0.074ns
  Clock Uncertainty:      0.148ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.027ns
    Discrete Jitter          (DJ):    0.080ns
    Phase Error              (PE):    0.093ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLK_375M_OBJ rise edge)
                                                      0.000     0.000 r  
    BUFR_X1Y9            BUFR                         0.000     0.000 r  FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
                         net (fo=55, routed)          0.255     0.255    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.447    -1.192 r  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.759    -0.433    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -0.407 r  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
                         net (fo=3, routed)           0.035    -0.372    FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.026    -0.346 r  FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
                         net (fo=164918, routed)      0.803     0.457    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
    OLOGIC_X0Y8          ODDR                                         r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y8          ODDR (Prop_oddr_C_Q)         0.192     0.649 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].oddr_inst/Q
                         net (fo=1, routed)           0.000     0.649    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/data_out_to_pins_int[0]
    AN30                 OBUFDS (Prop_obufds_I_O)     0.617     1.266 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[0].obufds_inst/O
                         net (fo=0)                   0.000     1.266    PVo_DAC1_DA_P[0]
    AN30                                                              r  PVo_DAC1_DA_P[0] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock Po_DAC1_DATCLKIN_P_obj rise edge)
                                                      0.000     0.000 r  
    BUFR_X1Y9            BUFR                         0.000     0.000 r  FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
                         net (fo=55, routed)          0.298     0.298    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.745    -1.447 r  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.823    -0.624    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030    -0.594 r  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
                         net (fo=3, routed)           0.039    -0.555    FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.030    -0.525 r  FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
                         net (fo=164918, routed)      1.064     0.539    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
    OLOGIC_X0Y30         ODDR (Prop_oddr_C_Q)         0.221     0.760 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/Q
                         net (fo=1, routed)           0.000     0.760    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_fwd_out
    AR34                 OBUFDS (Prop_obufds_I_O)     0.770     1.530 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/obufds_inst/O
                         net (fo=0)                   0.000     1.530    Po_DAC1_DATCLKIN_P
    AR34                                                              r  Po_DAC1_DATCLKIN_P (OUT)
                         clock pessimism             -0.074     1.456    
                         clock uncertainty            0.148     1.604    
                         output delay                -0.170     1.434    
  -------------------------------------------------------------------
                         required time                         -1.434    
                         arrival time                           1.266    
  -------------------------------------------------------------------
                         slack                                 -0.168    



report_timing -setup -to [get_ports PVo_DAC1_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date         : Fri Feb  9 15:00:06 2018
| Host         : SV2104 running 64-bit Service Pack 1  (build 7601)
| Command      : report_timing -setup -to [get_ports PVo_DAC1_DA_P]
| Design       : FSA_Main_wrapper
| Device       : 7vx485t-ffg1761
| Speed File   : -2  PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.368ns  (required time - arrival time)
  Source:                 FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].oddr_inst/C
                            (falling edge-triggered cell ODDR clocked by CLK_375M_OBJ  {rise@0.000ns fall@1.334ns period=2.667ns})
  Destination:            PVo_DAC1_DA_P[1]
                            (output port clocked by Po_DAC1_DATCLKIN_P_obj  {rise@0.000ns fall@1.334ns period=2.667ns})
  Path Group:             Po_DAC1_DATCLKIN_P_obj
  Path Type:              Max at Fast Process Corner
  Requirement:            1.334ns  (Po_DAC1_DATCLKIN_P_obj rise@2.667ns - CLK_375M_OBJ fall@1.334ns)
  Data Path Delay:        1.044ns  (logic 1.044ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUFDS=1)
  Output Delay:           0.570ns
  Clock Path Skew:        0.796ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.269ns = ( 3.936 - 2.667 ) 
    Source Clock Delay      (SCD):    0.547ns = ( 1.881 - 1.334 ) 
    Clock Pessimism Removal (CPR):    0.074ns
  Clock Uncertainty:      0.148ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.027ns
    Discrete Jitter          (DJ):    0.080ns
    Phase Error              (PE):    0.093ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLK_375M_OBJ fall edge)
                                                      1.334     1.334 f  
    BUFR_X1Y9            BUFR                         0.000     1.334 f  FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
                         net (fo=55, routed)          0.298     1.632    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.745    -0.113 f  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.823     0.710    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.030     0.739 f  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
                         net (fo=3, routed)           0.039     0.778    FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.030     0.808 f  FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
                         net (fo=164918, routed)      1.072     1.880    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
    OLOGIC_X0Y42         ODDR                                         f  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].oddr_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y42         ODDR (Prop_oddr_C_Q)         0.221     2.102 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].oddr_inst/Q
                         net (fo=1, routed)           0.000     2.102    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/data_out_to_pins_int[1]
    BA36                 OBUFDS (Prop_obufds_I_O)     0.823     2.924 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/pins[1].obufds_inst/O
                         net (fo=0)                   0.000     2.924    PVo_DAC1_DA_P[1]
    BA36                                                              r  PVo_DAC1_DA_P[1] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock Po_DAC1_DATCLKIN_P_obj rise edge)
                                                      2.667     2.667 r  
    BUFR_X1Y9            BUFR                         0.000     2.667 r  FSA_Main_i/selectio_LDV1/inst/clkout_buf_inst/O
                         net (fo=55, routed)          0.255     2.922    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.447     1.475 r  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.759     2.234    FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clk_out1_clk_wiz_0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     2.260 r  FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/inst/clkout1_buf/O
                         net (fo=3, routed)           0.035     2.295    FSA_Main_i/util_ds_buf_0/U0/BUFGCE_I[0]
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.026     2.321 r  FSA_Main_i/util_ds_buf_0/U0/USE_BUFGCE.GEN_BUFGCE[0].BUFGCE_U/O
                         net (fo=164918, routed)      0.796     3.117    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_in
    OLOGIC_X0Y30         ODDR (Prop_oddr_C_Q)         0.192     3.309 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/Q
                         net (fo=1, routed)           0.000     3.309    FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/clk_fwd_out
    AR34                 OBUFDS (Prop_obufds_I_O)     0.627     3.936 r  FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/obufds_inst/O
                         net (fo=0)                   0.000     3.936    Po_DAC1_DATCLKIN_P
    AR34                                                              r  Po_DAC1_DATCLKIN_P (OUT)
                         clock pessimism              0.074     4.010    
                         clock uncertainty           -0.148     3.862    
                         output delay                -0.570     3.292    
  -------------------------------------------------------------------
                         required time                          3.292    
                         arrival time                          -2.924    
  -------------------------------------------------------------------
                         slack                                  0.368


#-------------------------------------------------------------------------------------------------------------------------------------------------------
# HIGH SPEED ADC's - 375 MHz Differential Clock
#-------------------------------------------------------------------------------------------------------------------------------------------------------
#LDV1
create_clock -period 2.666 -name Pi_CH2_CLOCK_P_obj -waveform {0.000 1.333} [get_ports Pi_CH2_CLOCK_P_clk_p]


#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's  Clocks - SRS 1 - 17 - 2018 (Forwarded Clock is running at 375MHz)
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_generated_clock -name Po_DAC1_DATCLKIN_P_obj -source [get_pins FSA_Main_i/DAC1_LTC2000_0/U0/DAC1_LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/C] -divide_by 1 [get_ports Po_DAC1_DATCLKIN_P]
create_generated_clock -name Po_DAC2_DATCLKIN_P_obj -source [get_pins FSA_Main_i/DAC2_LTC2000_0/U0/LTC2000ACY_11_IF_U0/DAC_A_SELECTIO/inst/oddr_inst/C]      -divide_by 1 [get_ports Po_DAC2_DATCLKIN_P]

#-------------------------------------------------------------------------------------------------------------------------------------------------------
# MMCM  Clocks from MMCM are automatically generated, constraint is not necessary here
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_generated_clock -name CLK_375M_OBJ -source [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_in1] -divide_by 1 [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_out1]
create_generated_clock -name CLK_250M_OBJ -source [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_in1] -divide_by 3 -multiply_by 2 [get_pins FSA_Main_i/mmcm_rst_sync_0/U0/clk_wiz_inst/clk_out2]







#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's  set_output_delay's - SRS 1 - 17 - 2018
#-------------------------------------------------------------------------------------------------------------------------------------------------------
#  Double Data Rate Source Synchronous Outputs 
#
#  Source synchronous output interfaces can be constrained either by the max data skew
#  relative to the generated clock or by the destination device setup/hold requirements.
#
#  Setup/Hold Case:
#  Setup and hold requirements for the destination device and board trace delays are known.
#
# forwarded                        _________________________________
# clock                 __________|                                 |______________
#                                 |                                 |
#                           tsu_r |  thd_r                    tsu_f | thd_f
#                         <------>|<------->                <------>|<----->
#                         ________|_________                ________|_______
# data @ destination   XXX__________________XXXXXXXXXXXXXXXX________________XXXXX
#
# Example of creating generated clock at clock output port
# create_generated_clock -name <gen_clock_name> -multiply_by 1 -source [get_pins <source_pin>] [get_ports <output_clock_port>]
# gen_clock_name is the name of forwarded clock here. It should be used below for defining "fwclk".	



set fwclk_DAC1   		Po_DAC1_DATCLKIN_P_obj;     				# forwarded clock name (generated using create_generated_clock at output clock port) 
set fwclk_DAC2   		Po_DAC2_DATCLKIN_P_obj;     				# forwarded clock name (generated using create_generated_clock at output clock port)       
set tsu_r        		0.570;            							# destination device setup time requirement for rising edge (0.570)
set thd_r        		-0.170;            							# destination device hold time requirement for rising edge (-0.170)
set tsu_f        		0.570;            							# destination device setup time requirement for falling edge (0.570)
set thd_f        		-0.170;            							# destination device hold time requirement for falling edge (-0.170)
set trce_dly_max 		0.000;            							# maximum board trace delay
set trce_dly_min 		0.000;            							# minimum board trace delay
set output_port_DAC1 	{PVo_DAC1_DA_P PVo_DAC1_DB_P};   			# list of output ports
set output_port_DAC2 	{PVo_DAC2_DA_P PVo_DAC2_DB_P};   			# list of output ports

# Output Delay Constraints
set_output_delay -clock $fwclk_DAC1 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC1];
set_output_delay -clock $fwclk_DAC1 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC1];
set_output_delay -clock $fwclk_DAC1 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC1] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC1 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC1] -clock_fall -add_delay;

set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;

# Report Timing Template
# report_timing -rise_to [get_ports $output_ports] -max_paths 20 -nworst 2 -delay_type min_max -name src_sync_ddr_out_rise -file src_sync_ddr_out_rise.txt;
# report_timing -fall_to [get_ports $output_ports] -max_paths 20 -nworst 2 -delay_type min_max -name src_sync_ddr_out_fall -file src_sync_ddr_out_fall.txt;

 

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Re: How to set output delay for LTC2000A-11 DAC

I think this shows where the data needs to be valid at the DAC inputs.  If the data is held longer, after the clock edge, that would still meet the requirements.

 

 

timing diagram

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Re: How to set output delay for LTC2000A-11 DAC

So from the constraints point of view, nothing looks wrong. The tools are telling you that they cannot guarantee a -170ps hold time on a clock forwarded interface.

 

Since the clock and data take similar paths out of the FPGA, the net timing of the interface should be 0; the clock and data change at the same time (which is the equivalent of a 0 hold time). If this were the case, then your -170ps of hold would be satisfied.

 

However, the tools are doing "On Chip Variation" timing analysis. In the hold check, the source clock delay and datapath delay are the "fastest" they can be at a given process/voltage/temperature (PVT) corner, and the destination clock delay delay is the "slowest". The hold time check shown is at "Fast process corner", therefore the source clock and datapath delay are at true fastest PVT (called [FAST_MIN]) and the destination clock delay is at what is called [FAST_MAX]; the slowest that cells can be on a die that has some cells that are running at FAST_MIN.

 

When it does this analysis, it comes to the conclusion that the data can change as early as 338ps before the rising edge of the clock. This is too much variation to meet your -170ps hold time.

 

As a reference point, from the setup time analysis, we see that it can also change as late as 395ps after the clock. Basically around +/-350ps of clock data skew.

 

The tools are doing the "right thing" here. You may notice that the tool is ascribing different delays to the same component on the source clock delay (SCD) and the destination clock delay (DCD) - for example, the net from the MMCM to the first BUFG is 0.759ns in the SCD, but 0.823 in the DCD - this is clearly not correct since this is the same net. However, the tools "fix" this with the "clock pessimism" number - basically for each thing that is counted like this, it adds back the pessimism introduced by this - so it will actually add back in 66ps for this pessimism in this net.

 

However, there is some stuff that isn't common - the net from the final BUFGCTRL to the two different ODDRs, the two ODDRs and the two OBUFDSs are not in common, and the on die variation of these leads to the report of significant skew between these two nets (the -338ps to +395ps variation above).

 

So the tool reports this as a failure... Where do we go from here?

 

One option is to attempt to add additional (controlled) delay to the data output. I can't tell if these I/O are in a HR bank or an HP bank, but if they are in an HP bank you can use the ODELAY. With the ODELAY you could try and add around 200ps of delay to the data. This would make your hold time positive, and reduce your setup time by somewhat more than 200ps. But since you have 368ps of margin on the setup time, this could work.

 

If this is not an HP I/O then you can't use the ODELAY. You could try and do this with the MMCM; have it generate a second clock that is shifted forward by about 200ps and use that to clock the data and the original to clock the "clock" output (or you could go backwards instead, and have the clock come 200ps earlier). This will add the 200ps of delay you need, but now the clock paths to the two ODDRs share less in common, so the effective skew will be larger - maybe so large that you won't be able to satisfy both setup and hold at the same time.

 

The last thing we can do (and I always hesitate here) is ask ourselves the question "Is this reasonable". Is it reasonable that two I/O on the same bank at the same time can really vary by more than +/-350ps. They are on the same die, so have almost the same voltage (the IR drop can be a bit different), they are nearby so will have nearly the same temperature, and they are on the same die, so will have nearly the same process. Under these conditions is it reasonable to have so much skew (although the pins you use for clock and data don't seem all that close together in the bank).

 

According to the rules Xilinx uses, the tools say "yes - that is the skew". But I have always felt that they were too pessimistic on interfaces like this. For any cell that is in common between the two paths, the pessimism is completely removed. But if they aren't in common, the pessimism completely remains - even if they are immediately adjacent to each other on the die. This seems excessive.

 

So, (and this is pretty much the only place I ever recommend this) - you may just go with it. Yes, the tools say that the path fails, but...

 

I have a few other observations. Your clocking is "weird"...

 

First, the primary clock starts at a BUFR - that shouldn't happen; this only happens if you have a create_clock on an internal node of the FPGA (the BUFR) - you should never do that; constraints should always be applied to ports of the design (except for the TXOUTCLK and RXOUTCLK of a GT*).

 

Second, you have too many clock buffers on this path - you have the BUFR -> MMCM -> BUFG -> BUFG. Its hard for me to tell where the input to the BUFR comes from - maybe it is correct in your system. But for sure the two back to back BUFGs shouldn't be there. I can see that one is a BUFGCE, but even so, there should only be one BUFG in series; if you need both a gated and ungated clock, the BUFG and BUFGCE should be in parallel, not in series (see this post on using the BUFGCE). This stuff won't affect your timing of this path (since all of this is on the common clocking stuff), but you should have a clean clock architecture and clean constraints...

 

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Re: How to set output delay for LTC2000A-11 DAC

I made a smaller project that only includes the ADC selectio inputs and ADC clock, and the clocking strategy I have set up, the FIFO for collecting the data from the ADC and repeating the data out of the selectio outputs to the DAC.  I wanted to make a clear picture of my clocking strategy, so I could continue this conversation to find out if there is a better way to do what I think I need to do for the clocking strategy.  In doing so, since this small project only takes about 3 minutes to implement, I started adjusting the values in the set_output_delay constraints for the DAC in order to find out where the "window" is that meets timing.  The window I found aligns nicely with the timing required for the DAC if it is set to "Quadrature" mode rather than "In Phase" mode.  I modified the firmware to initialize the DAC in "Quadrature" mode, and made a build with the new constraints values that align with the quadrature mode timing, and I don't get timing errors for this part of the circuit now.  The requirements in "Quadrature" mode are +/- 200pS from the clock edge for setup and hold.  I tested this in the hardware, and the DAC's are still working properly.

 

Using quadrature mode and meeting timing, makes me believe that this will continue to work over the entire conservative operating range of the FPGA part, regarding voltage and temperature, etc., that the tools test the timing for.

 

My new timing constraints for the set_output_delay look like this now:

 

#-------------------------------------------------------------------------------------------------------------------------------------------------------
# High Speed DAC's  set_output_delay's - SRS 2 - 12 - 2018
#-------------------------------------------------------------------------------------------------------------------------------------------------------
#  Double Data Rate Source Synchronous Outputs 
#
#  Source synchronous output interfaces can be constrained either by the max data skew
#  relative to the generated clock or by the destination device setup/hold requirements.
#
#  Setup/Hold Case:
#  Setup and hold requirements for the destination device and board trace delays are known.
#
# forwarded                        _________________________________
# clock                 __________|                                 |______________
#                                 |                                 |
#                           tsu_r |  thd_r                    tsu_f | thd_f
#                         <------>|<------->                <------>|<----->
#                         ________|_________                ________|_______
# data @ destination   XXX__________________XXXXXXXXXXXXXXXX________________XXXXX
#
# Example of creating generated clock at clock output port
# create_generated_clock -name <gen_clock_name> -multiply_by 1 -source [get_pins <source_pin>] [get_ports <output_clock_port>]
# gen_clock_name is the name of forwarded clock here. It should be used below for defining "fwclk".	



set fwclk_DAC2   		Po_DAC2_DATCLKIN_P_obj;     				# forwarded clock name (generated using create_generated_clock at output clock port)       
set tsu_r        		0.867;            							# destination device setup time requirement for rising edge Quadrature (0.6667 + 0.200)
set thd_r        		-0.466;            							# destination device hold time requirement for rising edge Quadrature (-(0.6667 -0.200)
set tsu_f        		0.867;            							# destination device setup time requirement for falling edge (0.6667 + 0.200)
set thd_f        		-0.466;            							# destination device hold time requirement for falling edge (-(0.6667 -0.200)
set trce_dly_max 		0.000;            							# maximum board trace delay
set trce_dly_min 		0.000;            							# minimum board trace delay
set output_port_DAC2 	{PVo_DAC2_DA_P PVo_DAC2_DB_P};   			# list of output ports

# Output Delay Constraints

set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_r] [get_ports $output_port_DAC2];
set_output_delay -clock $fwclk_DAC2 -max [expr $trce_dly_max + $tsu_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;
set_output_delay -clock $fwclk_DAC2 -min [expr $trce_dly_min - $thd_f] [get_ports $output_port_DAC2] -clock_fall -add_delay;
Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Re: How to set output delay for LTC2000A-11 DAC

Regarding my "Weird" clocking, I want to understand this better, so I will try to explain what I have going on.

 

We have high speed ADC's running at 1.5GHz.  The ADC's send the LVDS differential data to the FPGA using DDR with a LVDS 375MHz differential clock.  We end up with two samples on each clock edge, or four samples for each period.

 

I am using a selectio interface wizard to collect the clock and data from the ADC.

 

The selectio interface wizard has a differential to single ended buffer for the incoming clock, and then uses a BUFR to send that clock out of the selectio interface wizard block.  That is the only option when using the selectio interface wizard ip.

 

The DSP systen that uses this data needs to run at the 375MHz clock, so I use a clocking wizard in MMCM mode to generate the DSP system clock.

 

I monitor the locked output in firmware.

 

Once the MMCM is locked, I enable a BUFG_CE that allows the clock to go out to the DSP system.

 

I hold the DSP system in reset until the MMCM is locked and the BUFG_CE is enabled.  The DSP system would sometimes lock up before we started using the BUFG_CE to hold off the clock until it was locked.

 

I have learned that there is a Safe Clock Startup check box in the clocking wizard that automatically does the same thing, and I may switch over to using that, that would get rid of having the two BUFG's in series. 

 

So, now I have a clock coming from the selectio interface wizard, and a DSP system clock from the MMCM.

 

I use the clock from the selectio interface wizard as the write clock to a FIFO, and the DSP system clock from the MMCM as the read clock to the FIFO.  I also have a separate control from the firmware for the rd_en and wr_en of the FIFO, with appropriate clock domain crossing circuitry for those signals.

 

In my timing constraints, I have the following which creates the clock coming in from the ADC:

#-------------------------------------------------------------------------------------------------------------------------------------------------------
# Clock input from High Speed ADC's
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_clock -period 2.666 -name Pi_CH2_CLOCK_P_obj -waveform {0.000 1.333} [get_ports Pi_CH2_CLOCK_P_clk_p]
set_input_jitter                                    [get_clocks -of_objects [get_ports Pi_CH2_CLOCK_P_clk_p]] 0.027

get_ports Pi_CH2_CLOCK_P_clk_p is the input pin ahead of the selectio interface wizard.

 

Here is the assigned pin in the constraint file:

set_property PACKAGE_PIN C35 [get_ports Pi_CH2_CLOCK_P_clk_p]

I then use a create_generated_clock to name the DSP system clock for use with other timing constraints.

#-------------------------------------------------------------------------------------------------------------------------------------------------------
# MMCM  Clocks from MMCM are automatically generated, constraint is not necessary here
#-------------------------------------------------------------------------------------------------------------------------------------------------------
create_generated_clock -name CLK_375M_OBJ -source [get_pins IP_Explore_i/clk_wiz_0/clk_in1] -divide_by 1 [get_pins IP_Explore_i/clk_wiz_0/clk_out1]

Does this make sense for where the input to the BUFR comes from?  Is there something else I can show you that would be helpful?

 

Here is a screenshot of what I am doing in the block design:

clocking.jpg

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Re: How to set output delay for LTC2000A-11 DAC

Here is a screen shot if I set the clk_wiz to safe clock startup

 

clocking_safe.jpg

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Observer sstadler
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Registered: ‎03-23-2016

Re: How to set output delay for LTC2000A-11 DAC

Here is the timing report using this small project. (In my large project, I'll change my clk_wiz to safe clock startup and verify it shows the same clocking as this report).  It looks like there is no longer the two BUFG's in series, so that cleans up one problem.

 

report_timing -setup -to [get_ports PVo_DAC2_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type max -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date         : Tue Feb 13 12:09:55 2018
| Host         : SV2104 running 64-bit Service Pack 1  (build 7601)
| Command      : report_timing -setup -to [get_ports PVo_DAC2_DA_P]
| Design       : IP_Explore_wrapper
| Device       : 7vx485t-ffg1761
| Speed File   : -2  PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.066ns  (required time - arrival time)
  Source:                 IP_Explore_i/selectio_wiz_1/inst/pins[5].oddr_inst/C
                            (rising edge-triggered cell ODDR clocked by CLK_375M_OBJ  {rise@0.000ns fall@1.334ns period=2.667ns})
  Destination:            PVo_DAC2_DA_P[5]
                            (output port clocked by Po_DAC2_DATCLKIN_P_obj  {rise@0.000ns fall@1.334ns period=2.667ns})
  Path Group:             Po_DAC2_DATCLKIN_P_obj
  Path Type:              Max at Fast Process Corner
  Requirement:            1.334ns  (Po_DAC2_DATCLKIN_P_obj fall@1.334ns - CLK_375M_OBJ rise@0.000ns)
  Data Path Delay:        1.010ns  (logic 1.010ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUFDS=1)
  Output Delay:           0.867ns
  Clock Path Skew:        0.779ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.194ns = ( 2.527 - 1.334 ) 
    Source Clock Delay      (SCD):    0.482ns
    Clock Pessimism Removal (CPR):    0.067ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.027ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.097ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLK_375M_OBJ rise edge)
                                                      0.000     0.000 r  
    BUFR_X1Y9            BUFR                         0.000     0.000 r  IP_Explore_i/selectio_wiz_0/inst/clkout_buf_inst/O
                         net (fo=48, routed)          0.298     0.298    IP_Explore_i/clk_wiz_0/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.745    -1.447 r  IP_Explore_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=2, routed)           0.823    -0.624    IP_Explore_i/clk_wiz_0/inst/clk_out1_IP_Explore_clk_wiz_0_0
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.030    -0.594 r  IP_Explore_i/clk_wiz_0/inst/clkout1_buf/O
                         net (fo=60, routed)          1.076     0.482    IP_Explore_i/selectio_wiz_1/inst/clk_in
    OLOGIC_X1Y8          ODDR                                         r  IP_Explore_i/selectio_wiz_1/inst/pins[5].oddr_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y8          ODDR (Prop_oddr_C_Q)         0.221     0.703 r  IP_Explore_i/selectio_wiz_1/inst/pins[5].oddr_inst/Q
                         net (fo=1, routed)           0.000     0.703    IP_Explore_i/selectio_wiz_1/inst/data_out_to_pins_int[5]
    BA22                 OBUFDS (Prop_obufds_I_O)     0.789     1.492 r  IP_Explore_i/selectio_wiz_1/inst/pins[5].obufds_inst/O
                         net (fo=0)                   0.000     1.492    PVo_DAC2_DA_P[5]
    BA22                                                              r  PVo_DAC2_DA_P[5] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock Po_DAC2_DATCLKIN_P_obj fall edge)
                                                      1.334     1.334 r  
    BUFR_X1Y9            BUFR                         0.000     1.334 r  IP_Explore_i/selectio_wiz_0/inst/clkout_buf_inst/O
                         net (fo=48, routed)          0.255     1.589    IP_Explore_i/clk_wiz_0/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.447     0.142 r  IP_Explore_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=2, routed)           0.759     0.901    IP_Explore_i/clk_wiz_0/inst/clk_out1_IP_Explore_clk_wiz_0_0
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.026     0.927 r  IP_Explore_i/clk_wiz_0/inst/clkout1_buf/O
                         net (fo=60, routed)          0.798     1.725    IP_Explore_i/selectio_wiz_1/inst/clk_in
    OLOGIC_X1Y28         ODDR (Prop_oddr_C_Q)         0.192     1.917 f  IP_Explore_i/selectio_wiz_1/inst/oddr_inst/Q
                         net (fo=1, routed)           0.000     1.917    IP_Explore_i/selectio_wiz_1/inst/clk_fwd_out
    AR23                 OBUFDS (Prop_obufds_I_O)     0.611     2.527 f  IP_Explore_i/selectio_wiz_1/inst/obufds_inst/O
                         net (fo=0)                   0.000     2.527    Po_DAC2_DATCLKIN_P
    AR23                                                              f  Po_DAC2_DATCLKIN_P (OUT)
                         clock pessimism              0.067     2.594    
                         clock uncertainty           -0.170     2.425    
                         output delay                -0.867     1.558    
  -------------------------------------------------------------------
                         required time                          1.558    
                         arrival time                          -1.492    
  -------------------------------------------------------------------
                         slack                                  0.066    




report_timing  -hold -to [get_ports PVo_DAC2_DA_P]
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Timing 38-78] ReportTimingParams: -to_pins  -max_paths 1 -nworst 1 -delay_type min -sort_by slack.
Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
| Date         : Tue Feb 13 12:10:23 2018
| Host         : SV2104 running 64-bit Service Pack 1  (build 7601)
| Command      : report_timing -hold -to [get_ports PVo_DAC2_DA_P]
| Design       : IP_Explore_wrapper
| Device       : 7vx485t-ffg1761
| Speed File   : -2  PRODUCTION 1.12 2014-09-11
------------------------------------------------------------------------------------

Timing Report

Slack (MET) :             0.100ns  (arrival time - required time)
  Source:                 IP_Explore_i/selectio_wiz_1/inst/pins[2].oddr_inst/C
                            (rising edge-triggered cell ODDR clocked by CLK_375M_OBJ  {rise@0.000ns fall@1.334ns period=2.667ns})
  Destination:            PVo_DAC2_DA_P[2]
                            (output port clocked by Po_DAC2_DATCLKIN_P_obj  {rise@0.000ns fall@1.334ns period=2.667ns})
  Path Group:             Po_DAC2_DATCLKIN_P_obj
  Path Type:              Min at Fast Process Corner
  Requirement:            0.000ns  (Po_DAC2_DATCLKIN_P_obj rise@0.000ns - CLK_375M_OBJ rise@0.000ns)
  Data Path Delay:        0.784ns  (logic 0.784ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (OBUFDS=1)
  Output Delay:           0.466ns
  Clock Path Skew:        0.981ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.447ns
    Source Clock Delay      (SCD):    0.399ns
    Clock Pessimism Removal (CPR):    0.067ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + TIJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.027ns
    Discrete Jitter          (DJ):    0.124ns
    Phase Error              (PE):    0.097ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLK_375M_OBJ rise edge)
                                                      0.000     0.000 r  
    BUFR_X1Y9            BUFR                         0.000     0.000 r  IP_Explore_i/selectio_wiz_0/inst/clkout_buf_inst/O
                         net (fo=48, routed)          0.255     0.255    IP_Explore_i/clk_wiz_0/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.447    -1.192 r  IP_Explore_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=2, routed)           0.759    -0.433    IP_Explore_i/clk_wiz_0/inst/clk_out1_IP_Explore_clk_wiz_0_0
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.026    -0.407 r  IP_Explore_i/clk_wiz_0/inst/clkout1_buf/O
                         net (fo=60, routed)          0.806     0.399    IP_Explore_i/selectio_wiz_1/inst/clk_in
    OLOGIC_X1Y42         ODDR                                         r  IP_Explore_i/selectio_wiz_1/inst/pins[2].oddr_inst/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y42         ODDR (Prop_oddr_C_Q)         0.192     0.591 r  IP_Explore_i/selectio_wiz_1/inst/pins[2].oddr_inst/Q
                         net (fo=1, routed)           0.000     0.591    IP_Explore_i/selectio_wiz_1/inst/data_out_to_pins_int[2]
    AL21                 OBUFDS (Prop_obufds_I_O)     0.592     1.183 r  IP_Explore_i/selectio_wiz_1/inst/pins[2].obufds_inst/O
                         net (fo=0)                   0.000     1.183    PVo_DAC2_DA_P[2]
    AL21                                                              r  PVo_DAC2_DA_P[2] (OUT)
  -------------------------------------------------------------------    -------------------

                         (clock Po_DAC2_DATCLKIN_P_obj rise edge)
                                                      0.000     0.000 r  
    BUFR_X1Y9            BUFR                         0.000     0.000 r  IP_Explore_i/selectio_wiz_0/inst/clkout_buf_inst/O
                         net (fo=48, routed)          0.298     0.298    IP_Explore_i/clk_wiz_0/inst/clk_in1
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -1.745    -1.447 r  IP_Explore_i/clk_wiz_0/inst/mmcm_adv_inst/CLKOUT0
                         net (fo=2, routed)           0.823    -0.624    IP_Explore_i/clk_wiz_0/inst/clk_out1_IP_Explore_clk_wiz_0_0
    BUFGCTRL_X0Y0        BUFGCTRL (Prop_bufgctrl_I0_O)
                                                      0.030    -0.594 r  IP_Explore_i/clk_wiz_0/inst/clkout1_buf/O
                         net (fo=60, routed)          1.067     0.473    IP_Explore_i/selectio_wiz_1/inst/clk_in
    OLOGIC_X1Y28         ODDR (Prop_oddr_C_Q)         0.221     0.694 r  IP_Explore_i/selectio_wiz_1/inst/oddr_inst/Q
                         net (fo=1, routed)           0.000     0.694    IP_Explore_i/selectio_wiz_1/inst/clk_fwd_out
    AR23                 OBUFDS (Prop_obufds_I_O)     0.753     1.447 r  IP_Explore_i/selectio_wiz_1/inst/obufds_inst/O
                         net (fo=0)                   0.000     1.447    Po_DAC2_DATCLKIN_P
    AR23                                                              r  Po_DAC2_DATCLKIN_P (OUT)
                         clock pessimism             -0.067     1.380    
                         clock uncertainty            0.170     1.549    
                         output delay                -0.466     1.083    
  -------------------------------------------------------------------
                         required time                         -1.083    
                         arrival time                           1.183    
  -------------------------------------------------------------------
                         slack                                  0.100    

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Observer sstadler
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Re: How to set output delay for LTC2000A-11 DAC

Well, I found, in my very large main design, when I was changing the design to use the MMCM with the safe clock startup and removing the extra BUFG_CE, that I had accidentally connected a portion of the circuit to the input side of the BUFG_CE, where it was all supposed to be connected to the output side of the BUFG_CE.  Perhaps this contributed to what showed up as weird?  If so, yep, that was a mistake, but now, at least that will be cleaned up.

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Historian
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Registered: ‎01-23-2009

Re: How to set output delay for LTC2000A-11 DAC

My new timing constraints for the set_output_delay look like this now

 

I don't understand how you came up with these numbers. You say you are now running in quadrature mode, which means that tsu=200ps and th=200ps. Yet, your constraint files are tsu=867 and th=-466 - these are not what are expected.

 

Furthermore, the output structure you have been describing, where forwarded clock and data come from ODDR/OSERDES running on the same clock are inconsistent with quadrature mode - the idea in quadrature mode is that the sending device sends a clock that is 90 degrees out of phase with the change in data - thus you need to use a 90 degree shifted clock for one or the other (and incur some additional uncertainties).

 

I also don't understand what you mean by "I started adjusting the delay values in the set_output_delay constraints" - the delay values come from the DAC datasheet - you don't "adjust" them unless you change the mode of the DAC (i.e. use Quadrature or not, and if not if you change DCKI_TADJ).

 

Avrum

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Observer sstadler
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Registered: ‎03-23-2016

Re: How to set output delay for LTC2000A-11 DAC

To come up with the window that meets timing, I increased the tsu_r and tsu_f until I didn't get a setup timing error, then I increased thd_r and thd_f until I didn't get a hold error.

 

The resulting values were tsu = 0.870 and thd = -0.370

 

You are correct, I confused myself, and I need to go back to In-Phase mode and increase the delay.

 

The max delay I can set is 570pS, where the default is 400pS.  So that is an increase of 170pS.

 

That would give me a tsu of 740pS and thd of -340pS.  I would need 30pS more delay to fully meet the conservative timing calculations that the tools are using.

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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Observer sstadler
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Re: How to set output delay for LTC2000A-11 DAC

I just re-tested in hardware using the In-Phase mode with the 570pS delay, and the signal out of the DACs looks perfect...

Steven R. Stadler PE
Senior Electrical Engineer
TSI Incorporated


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