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Scholar wzab
Scholar
324 Views
Registered: ‎08-24-2011

How to specify the phase relationship between two external clocks?

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I have a system that uses two external clocks. The first of them - CLK0 is directly delivered by a communcation device (so it has certain significant jitter, but is stable). The second one - CLK1 is a "jitter cleaned" copy of CLK0, so it has the same frequency, much smaller jitter and certain defined phase shift comparing to CLK0. Of course CLK1 is available only after the jitter cleaner circuit is configured and locked, and that's why both clocks are available in the system.

I need to specify the phase relationship between those two clocks, to ensure proper timing analysis. I tried to define the second one as a "generated clock":

 

create_clock -period 50.000 -name CLK_0 -waveform {0.000 25.000} [get_ports CLK_0]
set_input_jitter CLK_0 2.000
create_generated_clock -source [get_ports CLK_0] -edges {1 2 3} -edge_shift {5.0 5.0 5.0} [get_ports CLK_1]
set_input_jitter CLK_1 0.100

but then in the "Report Clock Interaction", I get the following output:

 

Zrzut ekranu z 2019-07-05 15-09-00.png

Vivado says that the timing is correct:

Zrzut ekranu z 2019-07-05 15-06-34.png

Does it mean that I should ignore the information from "Report Clock Interaction"? I'd definitely prefere to get the reliable infomation whether the CDC is correctly working assuming the phase relationship defined in the XDC.

Is there a better solution to describe such external related clocks than "create_generated_clock"?

I attach the simple "reproducer". It doesn't do anything useful but shows the problem.

Regards,
Wojtek

 

 

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1 Solution

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Historian
Historian
292 Views
Registered: ‎01-23-2009

Re: How to specify the phase relationship between two external clocks?

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So, first, I am surprised that your create_generated_clock command works - are you sure there is no warning associated with this?

In general, there is supposed to be a connection (through combinatorial or sequential logic) from the -source of the generated clock to the attachment point of the generated clock. Since both of them are primary inputs of the FPGA, the tool will not find this connection, and should (I thought) have generated a critical warning.

In Vivado all clocks are related by default. So from a static timing point of view, if you have two primary clocks (created by create_clock) on different ports (CLK_1 and CLK_2) then they will be related. Since they share the same clock period, the tools will (correctly) time paths between them as having a requirement of the period of the clock. It will also understand the portion of the clock skew internal to the FPGA when analyzing paths.

However, you need to define the portion of the skew outside the FPGA. You have a number of tools at your disposal.

You can modify the edges of the second clock

  • create_clock -period 5 -waveform {1.0 6.0} [get_ports CLK_2]

However, this states that CLK_2 follows CLK_1 with 1ns of delay with no uncertainty - that is probably unrealistic, there is almost certainly some variation in the delay through your jitter cleaner.

So you should consider using the set_clock_latency command. For example if the delay through your jitter cleaner is 1ns +/- 0.2ns then you can use the -waveform above, but use

  • set_clock_latency -min -0.2 -clock [get_clocks CLK_2]
  • set_clock_latency -max +0.2 -clock [get_clocks CLK_2]

This will give the tools a full understanding of the static timing relationship between the two clocks.

However, the report_clock_interaction report will still show this as an "unsafe" clock crossing. The "unsafe" determination is done purely based on structure - if a path exists (with no timing exceptions) between clocks that don't trace back to the same input of the FPGA, then they are unsafe. There is nothing you can do to convince the tool otherwise. What you are describing here (where the same clock source drives two different input pins of the FPGA) is the one condition where this structure is safe - you will have to ignore the warning from the clock interaction report.

Avrum

4 Replies
Scholar wzab
Scholar
319 Views
Registered: ‎08-24-2011

Re: How to specify the phase relationship between two external clocks?

Jump to solution

I have modified the relationship between the clocks so that it will be difficult or even impossible to meet the requirements:

create_clock -period 50.000 -name CLK_0 -waveform {0.000 25.000} [get_ports CLK_0]
set_input_jitter CLK_0 2.000
create_generated_clock -source [get_ports CLK_0] -edges {1 2 3} -edge_shift {1.0 1.0 1.0} [get_ports CLK_1]
set_input_jitter CLK_1 0.100

after that I indeed get the information about timing violations:

Zrzut ekranu z 2019-07-05 15-22-18.pngand the following report in the "Report Clock Interaction":

Zrzut ekranu z 2019-07-05 15-23-29.png

Does it mean, that indeed "create_generated_clock" is the right way to describe such related clock, and I should simply ignore the "No Common Node | Timed (unsafe)" info in the above report? Please note that this message is the same in the original case (with correct timing closure) and in the modified one.

Regards,
Wojtek

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Moderator
Moderator
304 Views
Registered: ‎03-16-2017

Re: How to specify the phase relationship between two external clocks?

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Hi @wzab , 

Based on  your interaction report there is a red color in between CDC CLK_0 and CLK_1 and it says no common node. 

Which means : The two clocks reported are considered related and timed as synchronous by default.It is reporting that the timing engine cannot guarantee that these clocks are synchronous in hardware, since it could not determine a common node between the two clock trees.

Both clk0 and clk1 are determined to be synchronous in Vivado bydefault. However, since clk0 and clk1 are input ports, there is no common node relationship between the two clocks. For this case, Vivado Design Suite cannot guarantee that the two clocks are synchronous.

Check UG 906 , page 296 for info. and resolution on it. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug906-vivado-design-analysis.pdf

 

Apart from it  i will say , you can take one master clock as an input of FPGA and feed it to MMCM and then do phase shifting as per your requirement . And then you can use two output clocks from the output of mmcm (one is normal clock and the other is phase shifted clock) . By doing this practice tool will understand that this is a synchronous CDC and yes you will not require create_generated_clock constraints as well,Only master clock's constraint (create_clock) will be require.  And then you can work accordingly with it. 

 

Regards,
hemangd

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Highlighted
Historian
Historian
293 Views
Registered: ‎01-23-2009

Re: How to specify the phase relationship between two external clocks?

Jump to solution

So, first, I am surprised that your create_generated_clock command works - are you sure there is no warning associated with this?

In general, there is supposed to be a connection (through combinatorial or sequential logic) from the -source of the generated clock to the attachment point of the generated clock. Since both of them are primary inputs of the FPGA, the tool will not find this connection, and should (I thought) have generated a critical warning.

In Vivado all clocks are related by default. So from a static timing point of view, if you have two primary clocks (created by create_clock) on different ports (CLK_1 and CLK_2) then they will be related. Since they share the same clock period, the tools will (correctly) time paths between them as having a requirement of the period of the clock. It will also understand the portion of the clock skew internal to the FPGA when analyzing paths.

However, you need to define the portion of the skew outside the FPGA. You have a number of tools at your disposal.

You can modify the edges of the second clock

  • create_clock -period 5 -waveform {1.0 6.0} [get_ports CLK_2]

However, this states that CLK_2 follows CLK_1 with 1ns of delay with no uncertainty - that is probably unrealistic, there is almost certainly some variation in the delay through your jitter cleaner.

So you should consider using the set_clock_latency command. For example if the delay through your jitter cleaner is 1ns +/- 0.2ns then you can use the -waveform above, but use

  • set_clock_latency -min -0.2 -clock [get_clocks CLK_2]
  • set_clock_latency -max +0.2 -clock [get_clocks CLK_2]

This will give the tools a full understanding of the static timing relationship between the two clocks.

However, the report_clock_interaction report will still show this as an "unsafe" clock crossing. The "unsafe" determination is done purely based on structure - if a path exists (with no timing exceptions) between clocks that don't trace back to the same input of the FPGA, then they are unsafe. There is nothing you can do to convince the tool otherwise. What you are describing here (where the same clock source drives two different input pins of the FPGA) is the one condition where this structure is safe - you will have to ignore the warning from the clock interaction report.

Avrum

Scholar wzab
Scholar
269 Views
Registered: ‎08-24-2011

Re: How to specify the phase relationship between two external clocks?

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Unfortunately, MMCM is not an option as the clocks are connected via external controllable PLL, the one responsible for "jitter cleaning".

Regards,
Wojtek

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