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How to verify the dynamic phase shift of clock

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Contributor
Posts: 47
Registered: ‎09-21-2016

How to verify the dynamic phase shift of clock

HI everyone,

 

I am trying to use the Dynamic phase shift option of the clock wizard. But, I don't know how to verify it.

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From the images, I am trying to compare CLKOUT1 with CLKOUT0. CLKOUT0 use phase shift configuration using "Use fine PS".

 

Form the user guide ,

Fvco = Fclkin * (M / D)

Fout = Fclkin * (M / D*O)

Phase shift increment = 1 / (56 * Fvco)

 

In my case, (clk_wiz_1)  Fclkin = 100 Mhz; so, FVco= 100 *(48/5) = 960Mhz; Fout = 960/12=80 MHZ; Phase increment ~ 18.6 ps

 

so, if I want to see a ~3ns phase shift, I need to give 1 to PSINCDEC for 163 PS_CLK cycle. So, the total increment will be 163*18.6 ~ 3ns.

 

but from my simulation result, I have no difference. Two clocks (CLKOUT0 and CLKOUT1) started from the same position 

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What am I missing? I also attached my top level code. 

 

There is another question. In the user guide, 7 series clock resources,2017, p.75,

"The number of PSCLK cycles is deterministic and is always 12 PSCLK cycles." I don't understand the meaning of this line.

 

Any suggestion will be very helpful.

 

Thank you

Rappy

 

 

Instructor
Posts: 3,546
Registered: ‎01-23-2009

Re: How to verify the dynamic phase shift of clock

[ Edited ]

So you have a number of issues here...

 

You are not using the PS interface correctly. The PS requirements are documented in UG472, Figure 3-7. Basically, you have to assert PSEN for one clock (only) with PSINCDEC indicating the direction, and wait for the shift to be complete, which can take up to 12(ish) clocks. Once the shift is done, the MMCM will assert PSDONE for one clock. Only after the PSDONE can you initiate another shift. You cannot leave PSEN asserted continuously.

 

Even with this, your waveform makes no sense - are you sure you are looking at the correct signals - the relationship between what you have marked as psen and psdone make no sense.

 

Next, what are you trying to do? Which clock do you want shifted with respect to which other clock, and how much do you want it shifted by. If you just want a fixed shift value, you don't need to use the PSEN/PSDONE/PSINCDEC interface -  just specify the phase shift you want in the clock wizard.

 

Next, you have selected CLKFBOUT_USE_FINE_PS. What this does is use the delay of the shifter for the PLL internal feedback clock. In essence, what that does is that for each positive shift of the fine phase shifter, the VCO compensates, and the net result is all output clocks shift back by this amount. You then also select the use_ps for clk_out1. This takes the VCO clock and shifts it forward by the same amount (there is only one dynamic shifter). So the net result is that clk_out1 will not be affected by the phase shift; the VCO will shift back and the clk_out1 will shift forward resulting in no change.

 

What will change, though, is that since clk_out2 does not have use_ps selected, every forward shift of the dynamic shifter will result in clk_out2 moving back by the shift increment - both with respect to the input clock and with respect to clk_out1.

 

Finally, it is generally not a good idea to cascade MMCMs together (which is what you did with the two Clocking Wizard cores). You seem to need 3 clocks, a 100MHz output clock and two 80MHz clocks, with some phase shift between them (its unclear exactly what relationship you need). All three of these clocks can (and should be) generated from a single MMCM - thus only one clocking wizard.

 

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