04-10-2017 12:22 AM
04-10-2017 12:36 AM
@xiaohu125 your issue seems to be the following clock mux:
BUFGCTRL_X0Y40 BUFGCTRL (Prop_BUFGCTRL_I0_O) 0.152 6.238 r u_data_conv/u_mem_mux/u_mux_app_clk/O X2Y3 (CLOCK_ROOT) net (fo=5444, routed) 2.697 8.935 u_data_conv/u_mem_mux/mig_app_clk
You need to understand why this mux exists and how to balance the clock skew caused by this mux.
04-10-2017 02:23 AM
I appreciate you quick reply.
I instantiate a bufgmux_ctrl primitive to switch between two MIG IP clocks, because in my design I intantiate two MIG IP Cores, each driving a DDR4 array of vcu108 board, to store as much data as possible. When there is not enough space to write into C1(memory array 1 on board) using u_mig_ddr4_c1, the design then switch to write into C2(memory array 2 on board) using u_mig_ddr4_c2.
04-10-2017 03:18 PM
@xiaohu125 Your current design is quite unorthodox. I think you should design a single MIG which uses all memory chips.
04-10-2017 07:13 PM
There are ten ddr4 components. One mig ip core can support up to 80bits wide, corresponding to five external ddr4 component, each is 16bits wide. So I have to use two mig ip cores to drive ten ddr4 components.