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xiaohu125
Contributor
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Registered: ‎06-13-2014

I dont know how to fix the intra-path timing violations of my design

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Hi,

 

Tool: vivado 2016.2

Board: VCU108

OS: Win7

 

I dont know how to resolve the intra-pach timing violations appeared in my design.

 捕获.PNG

The timing report is in attachment.

 

Anyone can help me?

 

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xiaohu125
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Registered: ‎06-13-2014
After removing the bufgctrl and use 'performance_explore' strategy, the issue is solved.

View solution in original post

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muzaffer
Teacher
Teacher
4,422 Views
Registered: ‎03-31-2012

@xiaohu125 your issue seems to be the following clock mux:

 

    BUFGCTRL_X0Y40       BUFGCTRL (Prop_BUFGCTRL_I0_O)
                                                      0.152     6.238 r  u_data_conv/u_mem_mux/u_mux_app_clk/O
    X2Y3 (CLOCK_ROOT)    net (fo=5444, routed)        2.697     8.935    u_data_conv/u_mem_mux/mig_app_clk

 You need to understand why this mux exists and how to balance the clock skew caused by this mux.

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xiaohu125
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Registered: ‎06-13-2014

Hi,@muzaffer

 

I appreciate you quick reply. 

 

I instantiate a bufgmux_ctrl primitive to switch between two MIG IP clocks, because in my design I intantiate two MIG IP Cores, each driving a DDR4 array of vcu108 board, to store as much data as possible. When there is not enough space to write into C1(memory array 1 on board) using u_mig_ddr4_c1, the design then switch to write into C2(memory array 2 on board) using u_mig_ddr4_c2.

 

捕获.PNG

 

1. If I don't use the BUFGCTRL to switch between mig_app1_clk and mig_app2_clk, Which method I can use to switch clock?
 
//==========================================================================
// mig_app_clk
//==========================================================================
BUFGMUX_CTRL u_mux_app_clk(
.O(mig_app_clk),
.I0(mig_app1_clk),
.I1(mig_app2_clk),
.S(flag_AppSW_dly)
);
 
2. Can I use the 'mig_app1_clk' to drive the 'mig_app2_wdf_data', 'mig_app2_rd_data' and etc signals? If yes, there is no need to use the BUFG_CTRL. 
4B541AE9%405CF93F28.7C42EB58_recompress.jpg
 
 
EE8B3B23%4051A3F950.7C42EB58_recompress.jpg
 
 
 
 
Regards
Xiaohu125
 
 
 
 
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muzaffer
Teacher
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Registered: ‎03-31-2012

@xiaohu125 Your current design is quite unorthodox. I think you should design a single MIG which uses all memory chips.

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xiaohu125
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Registered: ‎06-13-2014

Hi,@muzaffer

 

There are ten ddr4 components. One mig ip core can support up to 80bits wide, corresponding to five external ddr4 component, each is 16bits wide. So I have to use two mig ip cores to drive ten ddr4 components.

 

 

s.png

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xiaohu125
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Registered: ‎06-13-2014
After removing the bufgctrl and use 'performance_explore' strategy, the issue is solved.

View solution in original post

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h0-h0
Observer
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2,792 Views
Registered: ‎05-10-2017

So did you remove bufgctrl and use the same clock for both C1 and C2?

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