UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer retni
Observer
5,261 Views
Registered: ‎11-26-2010

I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

The arithmetic is:

 

s[n] = s[n-1]*(1-c) + din[n]*c

 

And I need it run in 200MHz, but the timing report showed it was not met the timing.

 

My sysgen project is this

 

How can I improve the timing?

sysgen.JPG
0 Kudos
1 Solution

Accepted Solutions
Instructor
Instructor
9,540 Views
Registered: ‎08-14-2007

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

What you have run into is a problem with Infinite Impulse Response (IIR) filters.  This is why FIR filters are more typically used in an FPGA: even though they are more complex to implement, they can easily be pipelined since they don't depend on the most recent output of the filter, only on the last N inputs to the filter.  You may be able to pipeline the IIR filter, however it becomes more complex.  For example, you could re-define the equation to use the output from two cycles earlier as well as the most recent two samples.  Depending on the logic used to implement the filter, this may or may not help you to meet timing, since it adds more layers of logic as well as adding an additional pipeline stage.

-- Gabor

View solution in original post

8 Replies
Xilinx Employee
Xilinx Employee
5,255 Views
Registered: ‎05-07-2015

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

HI @retni


Are you facing setup violations? 
If the violations are internal to addsub module,

How  are you implementing the Addsub module? using Fabric or DSP48?
Double click on the Addsub, in the implementation tab , check the pipeline for maximum performance option.

share your slx file here if possible.


Thanks
Bharath
--------------------------------------------------​--------------------------------------------
Please mark the Answer as "Accept as solution" if information provided addresses your query/concern.
Give Kudos to a post which you think is helpful.
--------------------------------------------------​-------------------------------------------
0 Kudos
Xilinx Employee
Xilinx Employee
5,250 Views
Registered: ‎08-02-2011

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

That's a combinatorial loop. In any case, it's not correct to your equation. You need a register in your feedback path before Cmult1. That should solve both problems.

www.xilinx.com
0 Kudos
Observer retni
Observer
5,242 Views
Registered: ‎11-26-2010

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

I have tried the Fabric and DSP48 option, but could not meet the timing neither.

this is my slx

 

thanks~

0 Kudos
Observer retni
Observer
5,241 Views
Registered: ‎11-26-2010

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

If I add a register before Cmult1, then the formula is not right, I think.

 

I have uploaded my .slx file before, can you please take a look at it? Thanks very much.

0 Kudos
Xilinx Employee
Xilinx Employee
5,221 Views
Registered: ‎08-02-2011

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

Hello,

 

s[n] = s[n-1]*(1-c) + din[n]*c

This means the current output sample is dependent on the previous output sample. So you need to store the previous output sample in a register and that feeds the mult and finally the adder. The way you have it now, the current output sample is feeding the mult/adder.

www.xilinx.com
0 Kudos
Observer retni
Observer
5,198 Views
Registered: ‎11-26-2010

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

The CMult1 has 1 clock delay itself. So I can not add register which will add another delay.

 

0 Kudos
Instructor
Instructor
9,541 Views
Registered: ‎08-14-2007

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

What you have run into is a problem with Infinite Impulse Response (IIR) filters.  This is why FIR filters are more typically used in an FPGA: even though they are more complex to implement, they can easily be pipelined since they don't depend on the most recent output of the filter, only on the last N inputs to the filter.  You may be able to pipeline the IIR filter, however it becomes more complex.  For example, you could re-define the equation to use the output from two cycles earlier as well as the most recent two samples.  Depending on the logic used to implement the filter, this may or may not help you to meet timing, since it adds more layers of logic as well as adding an additional pipeline stage.

-- Gabor

View solution in original post

Highlighted
Observer retni
Observer
5,146 Views
Registered: ‎11-26-2010

Re: I need to implement a arithmetic,but the timing is not met, how can I fix it?

Jump to solution

Thanks very much.

 

I use this equation to generate an adaptive threshold.

 

I think I can only run this algorithm on 100MHz on the zedboard....

0 Kudos