cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
rman12345
Visitor
Visitor
10,682 Views
Registered: ‎10-01-2013

IBUFG uses Local Routing Resources when BUFG does not

Jump to solution

I'm trying to send a clock through an IBUFG.  When I do this, I get this warning during PAR:

 

0 unrouted; WARNING:Route:466 - Unusually high hold time violation detected among 344 connections. The top 20 such instances are printed below.

 

All of the logic in question is synchronous, and doesn't even cross clock domains.  However I did notice that the tools are making the clock LOCAL.  All I did was change the IBUFG to a BUFG and now the clock uses a BUFGMUX and does not say LOCAL anymore, and my hold time violations are gone.

 

Two questions:

1. Does anyone have any idea why this is happening?

2. Is it a problem if I keep this as a BUFG rather than an IBUFG?

0 Kudos
1 Solution

Accepted Solutions
avrumw
Expert
Expert
17,539 Views
Registered: ‎01-23-2009

You have to understand the difference between the (confusingly named) IBUFG and the BUFG.

 

The IBUFG is nothing more than an IBUF. It is an input buffer that brings an external signal into the FPGA. There isn't really such a thing as an IBUFG, it is just a shorthand for telling the tool "Use an IBUF, and, by the way, I am planning to use this for a clock, so give me an error/warning if I try and LOC it to a pin that cannot be used for a clock"

 

Once the signal is inside the FPGA (the output of an IBUF or IBUFG), the signal is treated as a "regular" signal. It will be routed in regular fabric resources unless you tell the tool to do something else with it. In this case, you want to put it on a global clock route. To do this, you instantate a BUFG, which is a "global clock buffer".

 

In reality, what you want is to instantiate BOTH an IBUFG and then a BUFG. This is the configuration you really want.

 

When you changed your design to use only a BUFG (no IBUF or IBUFG), the tool inferred an IBUF for you; since the only way to bring an external signal (which is what input ports to your top level module are) is through an IBUF (or IOBUF). This IBUF was automatically inserted since there wasn't already one. If you look at the resulting schematic, you will see that your design has both an IBUF and a BUFG, regardless of the fact that you didn't instantiate an IBUF. While the tools can infer IBUFs (and OBUFs), it is recommended that you manually instantiate them.

 

Avrum

View solution in original post

2 Replies
smarell
Community Manager
Community Manager
10,668 Views
Registered: ‎07-23-2012
Hi,

The following are some scenarios that may cause this issue-

1.The clock net that drives the source and destination does not go through a BUFG
2. The source clock net goes through a BUFG but the destination clock doesn't
3.BUFG cascading on the clock net(s)
4.Other structures that bring high clock skew

If the clock is getting driven by IBUFG, then you need not use a BUFG. The difference between IBUFG and BUFG is that the IBUFG is present in the IOB tile of clock capable pins.

Please make sure that you aren't violating any of the above 4 points.

Regards,
Krishna
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos
avrumw
Expert
Expert
17,540 Views
Registered: ‎01-23-2009

You have to understand the difference between the (confusingly named) IBUFG and the BUFG.

 

The IBUFG is nothing more than an IBUF. It is an input buffer that brings an external signal into the FPGA. There isn't really such a thing as an IBUFG, it is just a shorthand for telling the tool "Use an IBUF, and, by the way, I am planning to use this for a clock, so give me an error/warning if I try and LOC it to a pin that cannot be used for a clock"

 

Once the signal is inside the FPGA (the output of an IBUF or IBUFG), the signal is treated as a "regular" signal. It will be routed in regular fabric resources unless you tell the tool to do something else with it. In this case, you want to put it on a global clock route. To do this, you instantate a BUFG, which is a "global clock buffer".

 

In reality, what you want is to instantiate BOTH an IBUFG and then a BUFG. This is the configuration you really want.

 

When you changed your design to use only a BUFG (no IBUF or IBUFG), the tool inferred an IBUF for you; since the only way to bring an external signal (which is what input ports to your top level module are) is through an IBUF (or IOBUF). This IBUF was automatically inserted since there wasn't already one. If you look at the resulting schematic, you will see that your design has both an IBUF and a BUFG, regardless of the fact that you didn't instantiate an IBUF. While the tools can infer IBUFs (and OBUFs), it is recommended that you manually instantiate them.

 

Avrum

View solution in original post