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andy.watts
Visitor
Visitor
8,608 Views
Registered: ‎08-02-2009

ISE/UCF Timing Constraints

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Hi,

 

I have shuffled things around in a previously working design and am having trouble with the following timing contraint.

 

 NET "clk_40m" TNM_NET = "clk_40m";
 NET "clk_64m" TNM_NET = "clk_64m";

 

TIMESPEC TS_clk_40m_to_clk_64m = FROM "clk_40m" TO "clk_64m" TIG;

 

This worked fine when these timing nets were in the top level implementation file but now they are another level down the build fails.

 

I have tried all obvious things such as:

 

 NET "sec_level_inst/clk_40m" TNM_NET = "clk_40m";

 

But I cannot get anything to work.

 

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vemulad
Xilinx Employee
Xilinx Employee
14,723 Views
Registered: ‎09-20-2012

Hi,

 

Open Technology schematic and find out the net name which is connected to clk_40m pin of submodule. Use this new net name in the UCF.

 

Thanks,

Deepika.

Thanks,
Deepika.
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vemulad
Xilinx Employee
Xilinx Employee
14,724 Views
Registered: ‎09-20-2012

Hi,

 

Open Technology schematic and find out the net name which is connected to clk_40m pin of submodule. Use this new net name in the UCF.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)

View solution in original post

0 Kudos