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mildred
Adventurer
Adventurer
504 Views
Registered: ‎03-22-2021

Ignoring paths on asynchronous resets

Hello,

I was wondering how to ignore the paths on my two asynchronous resets reset_n_100mhZ_rr and reset_n_200mhZ_rr

Each reset is asynchronous the first reset is used to reset modules clocked by CLK0_FPGA_100MHZ_i the second one is used to reset modules clocked by CLK0_FPGA_100MHZ_i 

I was planning to use these two constraints but i'm not sure they work

set_false_path -from [get_cells reset_n_100mhz_rr/C] -to [get_cells top_module_inst  ]

set_false_path -from [get_cells reset_n_200mhz_rr/C] -to [get_cells top_module_inst  ]

    --purpose: reset synchronisation
    p_sync_100 : process (CLK0_FPGA_100MHZ_i) is
    begin  -- process p_sync
        if rising_edge(CLK0_FPGA_100MHZ_i) then  -- rising clock edge
            reset_n_100mhz_r  <= RESET_N;
            reset_n_100mhz_rr <= reset_n_100mhz_r;
        end if;
    end process p_sync_100;

    RESET_N_100MHZ <= RESET_N and reset_n_100mhz_rr;


    --purpose: reset synchronisation
    p_sync_200 : process (CLK0_FPGA_200MHZ_i) is
    begin  -- process p_sync
        if rising_edge(CLK0_FPGA_200MHZ_i) then  -- rising clock edge
            reset_n_200mhz_r  <= RESET_N;
            reset_n_200mhz_rr <= reset_n_200mhz_r;
        end if;
    end process p_sync_200;

 

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6 Replies
hongh
Moderator
Moderator
503 Views
Registered: ‎11-04-2010

set_false_path -from [get_cells reset_n_100mhz_rr] -to [get_cells -hier -filter {IS_SEQUENTIAL ==1 && NAME =~ top_module_inst/*}  ]

set_false_path -from [get_cells reset_n_200mhz_rr] -to [get_cells -hier -filter {IS_SEQUENTIAL ==1 && NAME =~ top_module_inst/*  ]

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drjohnsmith
Teacher
Teacher
485 Views
Registered: ‎07-09-2009

As an aside,

 well done for synchronising the resets,  amazing how many don't,

   You have removed as many resets as possible form your code ?

https://www.xilinx.com/support/documentation/white_papers/wp272.pdf

 

One thought, 

  are the 100 and 200 clocks related to each other ?

       I was just wondering how your coping with the tools probably replicating this circuit in to a tree if its driving a lot of signals ?

I really try hard not to use a reset, 

    wonder if you should launder one reset of the other, 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
mildred
Adventurer
Adventurer
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Registered: ‎03-22-2021

Resets are related , they come from the same signal RESET_N

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avrumw
Expert
Expert
402 Views
Registered: ‎01-23-2009

set_false_path -from [get_cells reset_n_100mhz_rr] -to [get_cells -hier -filter {IS_SEQUENTIAL ==1 && NAME =~ top_module_inst/*}  ]
set_false_path -from [get_cells reset_n_200mhz_rr] -to [get_cells -hier -filter {IS_SEQUENTIAL ==1 && NAME =~ top_module_inst/*  ]

DO NOT DO THIS!

The whole point of the synchronizers that you showed is to synchronize the resets to the appropriate clock domain. And THESE ARE NEEDED. The resets to flip-flops must be synchronous to the clock - even the so-called "asynchronous preset/clear" inputs.

If you declare these as false paths then you will be rendering these synchronizers useless. The resets will then arrive at the flip-flops with no synchronous timing relationship to the clock resulting in untimed reset deassertions, which will result in your system being unreliable on the deasserting edge of reset.

Asynchronous reset inputs to flip-flops only mean that the reset condition can be asserted immediately - even if there is no clock. They MUST, however, be deasserted synchronously to the clock. Take a look a this post on the risks of not synchronizing your asynchronous reset

Avrum

mildred
Adventurer
Adventurer
389 Views
Registered: ‎03-22-2021

So i need to check that : if a flip-flop maintains the same state (under all conditions) during reset and on the first few clocks after reset is deasserted, then it will not exhibit a failure., if i want to keep these set_false_paths?

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drjohnsmith
Teacher
Teacher
342 Views
Registered: ‎07-09-2009

your reset is asynchronous to the 100 and the 200 mhz clock ?

  so the circuit to use is the input register and then a shift register, 

your doing an asynchronous to synchronous conversion.

It is a given that the 200 reset will de activate at a different time to the 100 Mhz rest.

    so hopefully yo have taken care of the data laundering.

 

If the 100 and the 200 are off the same orriginal clock,

    the way I would have doen things, is to only use the 200 Mhz clock, 

        and then made a divide by 2 to use as a 100 MHz enable, 

then everything is synchronous to the one clock, 

  

If the 100 and the 200 Are not off the same reference, then you need to have clock laundering circuits where the two meet,

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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