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Registered: ‎11-06-2019

Implementation WNS and TNS error

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Hi all.

Please suggest me what can be the possible reason for such a big difference in synthesis and implementation results of timing and resource utilization. Where exactly i need to look into to resolve it ?

Please refer the attached screenshot.

For synth: LUT 685, FF 972, no WNS and TNS.

For Implementation: LUT 47164, FF 57115, WNS -3.048, TNS -2023.678.

 

Waiting for your response.

Timing_error.JPG
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Registered: ‎11-04-2010

Re: Implementation WNS and TNS error

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Hi , @venugopal.kulkarni ,

To ignore the crossing clock domains paths, you can use the below 2 types:  (You can refer to UG903)

1.Example:

         set_false_paths -from [get_clocks CLKA ] -to [get_clocks CLKB]

         set_false_paths -from [get_clocks CLKB] -to [get_clocks CLKA ]

2. Example: 

     set_clock_groups -group CLKA -group CLKB

Important:For the paths ingored by timing constraints, you need to confirm the logic correctness by yourself.

    Ex: You can use Async FIFO or hand shaking to handle the crossing clock domains paths

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Registered: ‎11-04-2010

Re: Implementation WNS and TNS error

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Hi, @venugopal.kulkarni ,

Maybe most of your logic are in IP core, which is not shown in your synth utilization.

For the timing, could you open the detailed timing report to show data/clock path.

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Registered: ‎11-06-2019

Re: Implementation WNS and TNS error

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Do you want Inter-Clock Paths, Intra-clock paths and other path groups?
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Registered: ‎11-04-2010

Re: Implementation WNS and TNS error

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If possible, please upload the timing.rpx file.

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tt2.png
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Registered: ‎11-06-2019

Re: Implementation WNS and TNS error

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For me this save option is not there.
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Registered: ‎11-06-2019

Re: Implementation WNS and TNS error

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PFA

 

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Registered: ‎11-04-2010

Re: Implementation WNS and TNS error

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Hi, @venugopal.kulkarni ,

You fail to handle the cross clock domain paths properly.

You can see the unreasonable small requirement between 2 clock domains.

You need check your timing exception constraints for the above paths.

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tt3.png
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Registered: ‎11-06-2019

Re: Implementation WNS and TNS error

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Please suggest me the constraints that i need to include and also the format how to include it.
It will be a good help.
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Registered: ‎11-04-2010

Re: Implementation WNS and TNS error

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Hi , @venugopal.kulkarni ,

To ignore the crossing clock domains paths, you can use the below 2 types:  (You can refer to UG903)

1.Example:

         set_false_paths -from [get_clocks CLKA ] -to [get_clocks CLKB]

         set_false_paths -from [get_clocks CLKB] -to [get_clocks CLKA ]

2. Example: 

     set_clock_groups -group CLKA -group CLKB

Important:For the paths ingored by timing constraints, you need to confirm the logic correctness by yourself.

    Ex: You can use Async FIFO or hand shaking to handle the crossing clock domains paths

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Registered: ‎11-04-2010

Re: Implementation WNS and TNS error

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Hi, @venugopal.kulkarni ,

The content after get_clocks should be a clock name, instead of a pin name.

You can get the clock with the command after opening the synthesized/implemented design with the below command in TCL CONSOLE:

report_clocks

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