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dbrent
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Registered: ‎02-05-2019

Incorrect setup/hold times in datasheet report

I recently sumitted a question regarding arcs between OBUFT and IBUF being automatically cut by Vivado in loopback paths from an IOB output register to an IOB input register.

Can-timing-paths-arcs-from-OBUFT-O-to-IBUF-I-be-enabled 

As a workaround for this issue I attempted to use setup/hold times for the IOB input registers taken from the datasheet report to create output delay constraints for the IOB output registers but I believe the IOB input register setup/hold times are incorrectly reported in the datasheet

As an example (see report excerpts below), the setup time with respect to clk_fpga_0 for the FIFOs_HFb input should be 0.948 - 2.666 = -1.718 instead of 4.648 and the hold time should be 1.566 - 0.177 = 1.389 instead of -0.844. Note that clk_fpga_0 is 100MHz and there's a multicycle 2 constraint from RCLK, a 100MHz ODDR clock output with -6ns phase shift, and clk_fpga_0.

Thanks,

Dave Brent

 

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dbrent
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Registered: ‎02-05-2019

Correction: The last sentence should end in "to clk_fpga_0".

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