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Scholar mistercoffee
Scholar
862 Views
Registered: ‎04-04-2014

Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Hi,

I have a clock crossing FIFO and a critical warning about one of it's autogenerated OOC constraints. The OOC constraint file has the following:

set wr_clock [get_clocks -of_objects [get_ports wr_clk]]
set rd_clock [get_clocks -of_objects [get_ports rd_clk]]
set wr_clk_period [get_property PERIOD $wr_clock]
set rd_clk_period [get_property PERIOD $rd_clock]
set skew_value [expr {(($wr_clk_period < $rd_clk_period ) ? $wr_clk_period : $rd_clk_period) } ]

However, there are two possible clocks connected to the wr_clk pin of the FIFO. This because the wr_clk comes from an MMCM with a selectable input clock (CLKIN1/CLKIN2). Both of these clocks have a 4ns period, so wr_clock is actually a list of clocks and wr_clk_period has the value {4.000 4.000}, i.e. it's a list.

This skew_value is used in a constraint further down and this generates an error because a list of clock periods is not a value value for this constraint.

How do I fix this? The constraint file is autogenerated as OOC so I can't edit it beforehand? Given that the two MMCM clock input are the same period, should I tell the timing analyzer to only use one of them? They have similar paths up to the MMCM (CC pin to IBUFGDS to MMCM).

 

Thanks

 

 

 

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Historian
Historian
780 Views
Registered: ‎01-23-2009

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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I am using FIFO Generator v13.1 with Vivado 2017.2. It is configured with Native Ports as Independent Clocks Block Ram

I don't remember exactly when this was fixed, but this version is over 18 months old.

If you want to verify that this has been fixed before you make the decision to upgrade, make a copy of your project and try and load that into the latest version of Vivado and upgrade the FIFO IP. You should then be able to see the new constraints - I highly suspect that you will see that it now uses the get_property -min command.

Avrum

 

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13 Replies
Scholar mistercoffee
Scholar
852 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Also, if the answer is the latter (tell timing analyzer to only use one of the MMCM input clocks) how do I do this? So far I can't see anything specific for this, so put a false path on one of the clock inputs to the MMCM? This feels wrong.....

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Historian
Historian
840 Views
Registered: ‎01-23-2009

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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This is a pretty common occurrence and there is a standard solution to it...

set wr_clk_period [get_property -min PERIOD $wr_clock]
set rd_clk_period [get_property -min PERIOD $rd_clock]

 This way the "get_property" command always returns a number, not a list.

In fact, you can even go

set skew_value [get_property -min PERIOD "$wr_clock $rd_clk"]

to do the whole thing in one line.

Avrum

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Scholar mistercoffee
Scholar
827 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Yeah, I realise there is a fix but this is autogenerated ooc constraints, generated by the xilinx FIFO IP, it's not my constraint. Therefore, I can't change it.

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Scholar mistercoffee
Scholar
806 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Is it possible to suppress/disable IP generated ooc constraints at synthesis time? This way I could potentially created a modified version of this seemingly buggy xdc and override it?

As it stands this partiocular IP constraint is not being applied, due to the invalid value being given to the constraint. Obviously I could just add the modified line to my xdc (not ooc) and point it at the right part of logic to ensure it takes, but I'm still going to have an array of critical errors every time I build from the IP ooc constraint file, unless I am able to disable it.

any ideas?

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Scholar mistercoffee
Scholar
803 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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 I have had a search round, I think the last post here is most relevant to me:

Overriding default IP_ooc.xdc constraints?

He explains how to override the default IP constraints. I might attempt to do this in my flow somehow.

 

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Historian
Historian
791 Views
Registered: ‎01-23-2009

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Yeah, I realise there is a fix but this is autogenerated ooc constraints, generated by the xilinx FIFO IP, it's not my constraint. Therefore, I can't change it.

How old is the version of the FIFO generator that you are using???

This was a known problem of the FIFO generator constraints, but (as far as I remember) was fixed many years back. In fact, the addition of the -min option to the get_property command (which is not standard XDC) was added almost specifically for the FIFO generator (since this error kept creeping up over and over again).

If you are using an older version of the FIFO then the solution is simple - upgrade to a newer version.

If this is a new version of the FIFO generator, then please post the details of the tool version, the FIFO generator version, and maybe even post the .xci file for the FIFO - again, this bug was supposed to have been fixed a long time ago...

Avrum

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Scholar mistercoffee
Scholar
788 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Ok Sure.

I am using FIFO Generator v13.1 with Vivado 2017.2. It is configured with Native Ports as Independent Clocks Block Ram

Thanks

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Historian
Historian
782 Views
Registered: ‎01-23-2009

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Is it possible to suppress/disable IP generated ooc constraints at synthesis time? This way I could potentially created a modified version of this seemingly buggy xdc and override it?

Careful - I highly suspect that your problem is not with the ooc constraints, but the "regular" constraints (the non-OOC constraints).

The OOC constraints are only used when the block is synthesized "out-of-context" (which is the default). These supply information about the expected clock frequencies and some other context information for the FIFO when it is synthesized.

Once synthesized, though, the IP core is integrated into the top level design. At this point the OOC constraints are irrelevant (and are no longer used or have any effect) since the rest of the FPGA is now providing the "context" for the IP. In fact, it is specifically because of this that you have a problem - OOC the wr_clock has a single value provided by the ooc constraints. Once integrated the wr_clock has two constraints due to the fact that the IP is fed from an MMCM that does clock multiplexing.

Avrum

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Scholar mistercoffee
Scholar
781 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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XCI attached

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Historian
Historian
781 Views
Registered: ‎01-23-2009

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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I am using FIFO Generator v13.1 with Vivado 2017.2. It is configured with Native Ports as Independent Clocks Block Ram

I don't remember exactly when this was fixed, but this version is over 18 months old.

If you want to verify that this has been fixed before you make the decision to upgrade, make a copy of your project and try and load that into the latest version of Vivado and upgrade the FIFO IP. You should then be able to see the new constraints - I highly suspect that you will see that it now uses the get_property -min command.

Avrum

 

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Scholar mistercoffee
Scholar
777 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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Ok, I understand what you're saying. I don't quite understand how I have the problem then. There are meant to be two possible clocks on that net (even though they have the same period).

My design has changed slightly in that my clock now comes from a BUFGCTRLMUX with two inputs, rather than MMCM with muxed input, but the problem remains. Adding the -min option in the xdc does remove the critical warnings during synthesis by the way.

 

 

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Scholar mistercoffee
Scholar
769 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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@avrumw wrote:

I am using FIFO Generator v13.1 with Vivado 2017.2. It is configured with Native Ports as Independent Clocks Block Ram

I don't remember exactly when this was fixed, but this version is over 18 months old.

If you want to verify that this has been fixed before you make the decision to upgrade, make a copy of your project and try and load that into the latest version of Vivado and upgrade the FIFO IP. You should then be able to see the new constraints - I highly suspect that you will see that it now uses the get_property -min command.

Avrum

 


Ok, fair enough, but there is zero chance we will upgrade right now. We are a team of 2 FPGA designers in a company of 30 people. We are in the middle of a project with tight deadlines and last time we upgraded we ended up having to change our entire project flow which caused considerable pain. Also, as our license would only run to 2017.4 we'd likely have to purchase new ones. 

If the fix is the -min option I will persevere with replacing the xdc with a modified version. If it's another constraint issue I will have to fix it.

Thanks

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Scholar mistercoffee
Scholar
754 Views
Registered: ‎04-04-2014

Re: Invalid Option for skew_value on FIFO (multiple clocks on wr_clk pin)

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I have had a further thought, I'm not sure this particular constraint file is an OOC constraint xdc. The name of the file is IP_NAME_clocks.xdc, and doesn't contain the _ooc at the end like some of the other xdcs.

If so, then it would suggest it is this file that is the problem, as opposed to another constraint issue as you hypothesized (based on me claiming it was ooc...).

Thanks

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