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Registered: ‎05-22-2018

JESD SYNC~ Output Delay Constraints

I have a JESD interface in my FPGA (Zynq UltraScale+ MPSoC, xczu19eg-ffvc1760-1-i) I am using to communicate with a Texas Instruments ADS54J60 ADC. After running my FPGA design through implementation, Vivado gave critical warnings in the timing report saying two of the JESD ports going to the ADC did not have output delays. It also marked the severity of these missing constraints as “High”. I am currently trying to constrain these JESD outputs from my FPGA, specifically the SYNC~ signals (adc1_syncn and adc2_syncn). However, I am having trouble determining the proper reference clock and delay values.




The SYNC~ signal is sent from the FPGA using a clock running at 204.8 MHz. It is then clocked in by the ADC chip, which has a device clock of 819.2 MHz and a derived internal LMFC clock of 10.24 MHz. All of these clocks are synchronous to each other.


From the ADC datasheet, it appears the LMFC clock running at 10.24 MHz clocks in the SYNC~ signal (as shown in the waveform below). I am then lead to believe the LMFC clock should be the reference clock for the SYNC~ output delay. However, the only setup and hold delay values provided by the datasheet are in reference to the SYSREF signal (shown in the table below), which is ignored after its first pulse is used to synchronize the LMFC clock.






I have a few questions:


1) For the JESD interface, is the SYNC~ signal really clocked in by the LMFC clock? And if so, is this the correct clock to use to set output delay constraints?


2) If the LMFC clock is the correct clock to use for output delays, how can its associated setup and hold times be determined if the datasheet only provides setup and hold times in reference to the SYSREF input?

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