01-19-2017 07:48 AM
I have a problem with large clock skew. My clock comes from a MMCE is distributed. The fanout from the this output buffer is fo= 2500 which results in large arrival clock delay and lots of hold timing violations. By the synth_design with the hierarchy rebuilt I can work round the issue however I would rather not do this.
I can't obtain timing closure otherwise.
01-19-2017 08:57 AM
I am having trouble following some details in your post...
Is the clock from an "MMCM", and if so, what kind of buffer do you use on the output of the MMCM (it pretty much needs to be a BUFG or a BUFH). Is there more than one clock involved, or is the skew on the same clock.
A properly designed FPGA should have very little clock skew; the clock trees are all very well balanced, and have only a few hundred picoseconds of worst case skew - in general this is small enough to not create any problems for a design.
If you are having trouble, then, more likely, there is a problem with how your clock system is constructed...
You should tell use more about the problem - what device, what tool, what frequencies. Most importantly, you should give us details about your clock management, and post a timing report for the failed path. We can probably tell you more with this information.
01-19-2017 11:32 PM
Yes in addition to explaing what exactly is the BUffer used post MMCM (BUFG as we assume?),
could you also please elaborate on how hierarchy rebuilt option is helping on reducing the fanout of the clock buffer and there reduce the clock insertion delay?
please Share timing reports if possible.