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Contributor
Contributor
9,143 Views
Registered: ‎09-15-2008

Locating an XPS project timing error?

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I'm working on a pretty complex XPS project with a lot of custom peripherals, and the end of the design phase is in sight! Unfortunately, a couple of recent additions have caused my design to report a timing error on one net (as reported by the timing analyzer when I do a hardware build).

 

The build process tells me which constraint is violated but not which net violates it! How can I track this down? :(

 

Thanks,

Nick

 

 

Message Edited by nrclark on 04-09-2009 06:33 PM
Message Edited by nrclark on 04-09-2009 06:34 PM
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Xilinx Employee
Xilinx Employee
10,683 Views
Registered: ‎08-13-2007

Re: Locating an XPS project timing error?

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Nick,

 

Check the static timing analysis report file  -  the [designname].twr file (e.g. implementation\system.twr) for more details.

 

bt

 

Message Edited by timpe on 04-10-2009 12:44 PM
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Xilinx Employee
Xilinx Employee
10,684 Views
Registered: ‎08-13-2007

Re: Locating an XPS project timing error?

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Nick,

 

Check the static timing analysis report file  -  the [designname].twr file (e.g. implementation\system.twr) for more details.

 

bt

 

Message Edited by timpe on 04-10-2009 12:44 PM
Contributor
Contributor
9,109 Views
Registered: ‎09-15-2008

Re: Locating an XPS project timing error?

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Whoah, that file contains pretty much all I need to know!

 

I run about a quarter of my design off of a 10MHz GPS-synched timing clock, which I first run through a high-speed averaging filter to reject line noise the clock signal picks up as it arrives at the chassis where my board lives.

 

Unfortunately, the timing analyzer (and I would assume by extension the mapper and PAR) treats the signal like it's still in the high-speed clock domain. How can I manually add a constraint to this particular net to tell the tools that it's a low-speed clock?

 

I've attached the relevant portion of my timing report below.

 

================================================================================
Timing constraint: TS_clock_manager_100MHz_clock_manager_100MHz_DCM0_CLK_OUT_0_
= PERIOD TIMEGRP        
"clock_manager_100MHz_clock_manager_100MHz_DCM0_CLK_OUT_0_"        
TS_CLK_100MHZ_pin HIGH 50%;

 167745 paths analyzed, 21870 endpoints analyzed, 1 failing endpoint
 1 timing error detected. (1 setup error, 0 hold errors)
 Minimum period is  10.348ns.
--------------------------------------------------------------------------------
Slack:                  -0.174ns (requirement - (data path - clock path skew + uncertainty))
  Source:               timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT1 (FF)
  Destination:          chassis_controller_irig_clock_0/chassis_controller_irig_clock_0/USER_LOGIC_I/myFilter/buffer_10MHz_0 (FF)
  Requirement:          5.000ns
  Data Path Delay:      5.114ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         SRAM_CLOCK_pin_OBUF rising at 0.000ns
  Destination Clock:    SRAM_CLOCK_pin_OBUF falling at 5.000ns
  Clock Uncertainty:    0.060ns

  Clock Uncertainty:          0.060ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.000ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.120ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT1 to chassis_controller_irig_clock_0/chassis_controller_irig_clock_0/USER_LOGIC_I/myFilter/buffer_10MHz_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X50Y114.YQ     Tcko                  0.360   timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT1
                                                       timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT1
    BUFGCTRL_X0Y3.I0     net (fanout=1)        0.621   timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT1
    BUFGCTRL_X0Y3.O      Tbgcko_O              0.900   timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT_BUFG
                                                       timing_clock_filters_0/timing_clock_filters_0/my10mhzFilter/CLK_OUT_BUFG
    SLICE_X51Y114.BX     net (fanout=315)      2.902   CLK_10MHZ
    SLICE_X51Y114.CLK    Tdick                 0.331   chassis_controller_irig_clock_0/chassis_controller_irig_clock_0/USER_LOGIC_I/myFilter/buffer_10MHz<0>
                                                       chassis_controller_irig_clock_0/chassis_controller_irig_clock_0/USER_LOGIC_I/myFilter/buffer_10MHz_0
    -------------------------------------------------  ---------------------------
    Total                                      5.114ns (1.591ns logic, 3.523ns route)
                                                       (31.1% logic, 68.9% route)

--------------------------------------------------------------------------------

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Xilinx Employee
Xilinx Employee
9,107 Views
Registered: ‎08-13-2007

Re: Locating an XPS project timing error?

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You can add a multi-cycle path for elements that don't actually change every period.

More details on this and other timing constraints are available here:

http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf (Xilinx Timing Constraints User Guide)

Cheers,

bt

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Contributor
Contributor
9,098 Views
Registered: ‎09-15-2008

Re: Locating an XPS project timing error?

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Thanks, I'll read up on this.
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