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ofer.bahar
Contributor
Contributor
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Registered: ‎03-07-2014

MIG 7 Series on KC705 with single ended clock input

Hello

 

I have hold slack violatoins on the MIG7 with an embedded system on the KC705 and the system clock to the MIG7 is a single ended comming from an output of clocking_wizard (200Mhz) 

 

The 1'st hold slack is between source: phaser_out/OCLK to serdes_dq_i/RST

the 2'nd one is on the ref_clock to serdes_clock_div

 

on the summary of the 1'st one i see : Multicycle setup -start 2 and Hold -start 2

 

when i do the following tcl commands

 

set_multicycle_path -through [get_pins -filter {NAME =~ */OSERDESRST} -of [get_cells -hier -filter {REF_NAME == PHASER_OUT_PHY}]] -hold 2 -start

 

set_min_delay -from [get_clocks {u_system_mig_7series_0_0_mig/mem_refclk}] -to [get_clocks {u_system_mig_7series_0_0_mig/mem_refclk}] -0.3

 

the two vilations are solved - but i can not put them as constant exceptions in any xdc file

 

any help is appreciated ...

 

Ofer

 

Synthesis_violations.png
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3 Replies
ofer.bahar
Contributor
Contributor
11,016 Views
Registered: ‎03-07-2014

Hi

 

after solving the synthesis vilation and continue to imlementation, i had the 'Place 30-575 Sub optimal placement...' error - see attachment 

 

can it be the requirement to locate the sys_clk in the same column of the phy ?

 

Ofer

implementation_errors.png
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blaine
Xilinx Employee
Xilinx Employee
10,983 Views
Registered: ‎04-11-2008

Hi Ofer,

 

Have you added the source to the project instead of the XCI file?

 

When you add the XCI file to the project, the constraints are taken care of. Under the hood we scope constraints to the level of hierarchy that the IP core is in. This way the user does not need to worry about adding the full hierarchy path to the constraints.

 

During MIG generation, you should be able to generate an interface for the board if you ensure you have the board flow selected when you select the device for the project.

 

John

 

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ofer.bahar
Contributor
Contributor
10,941 Views
Registered: ‎03-07-2014

Hi John

 

I do not quite understand why you are asking if i added the source or xci to the design, maybe your asked it because i didn't mentioned that i use Vivado 2013.4 in project mode, and i just added the MIG7 IP to the design (the bd) in the IPI, so i do not if it added the source or the xci file.

 

But for now, non of the things i tried solved this one, so eventually i used the clock_system connected to the MIG7 differential input and used the MIG7 feature of it's mmce to add my additional required clocks, and after some small timing constraints (mainly for the clock to clock) the system works.

 

I still do not know ehhat can solve my original problem

 

Thanks

 

Ofer

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