MMCM clock skew causing huge hold violations

[Harish_Algat]

TIMING #3 Warning There is a large inter-clock skew of 5.504 ns between U_def_top/core/tile/InstructionQueue/ram_1_inst_opc_reg[4]/C (clocked by FOUTPOSTDIV_clk_wiz_0) and U_deftop/core/tile/core/exa__inst_opc_reg[4]/D (clocked by FOUTPOSTDIV_clk_wiz_0) that results in large hold timing violation(s) of -5.059 ns. Fixing large hold violations during routing might impact setup slack and result in more difficult timing closure

I have such warnings and have huge hold violations in the timing report..

is there a way U can fix this?

[hemangd]

@Harish_Algat 

This DRC warning is reporting that the large hold violation due to the inter-clock skew will most likely be difficult to close timing during implementation. It is recommended to investigate the large inter-clock skew greater than 1.0 ns to ensure proper constraints or design topology.

Hence, this is an issue due to the under-constarined design. 

Resolution:

Investigate whether the large inter-clock skew on the timing path should be timed or is related to non-optimal timing constraints. If the large skew occurs due to an unconstrained CDC path, add the necessary timing exception. If the violation occurs due to a logic associated with the clock tree, investigate the topology of path for improvements to more easily close timing. 

If the above information does not help then, provide the report timing summary txt file by running report_timing_summary <filepath>/timing.txt in tcl console after running opt_design (before place and route) .