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jmcano
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Registered: ‎06-05-2013

MMCME2_BASE: problem to derive a clock of an specific frequency

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I am using a KC705 (Kintex 7) Evaluation Board with Vivado 2013.1. 

 

I need two clocks, one at 1MHz and the other at 50MHz. To achieve this I use the 200MHz oscillator in the evaluation board, and the primitive MMCME2_BASE. 

 

All seems to be right in RTL Evaluation and Synthesis. But when trying to make a post-synthesis timing simulation, it fails with this message. 

 

Attribute Syntax Error : The calculation of VCO frequency=100.000000 Mhz. This exceeds the permitted VCO frequency range of 600.000000 Mhz to 1600.000000 Mhz. The VCO frequency is calculated with formula: VCO frequency =  CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range.

 

The problem is that to reach 600MHz, given that CLKIN1 is the 200MHz oscillator (period 5ns), CLKFBOUT_MULT_F / DIVCLK_DIVIDE must be at least 3. But in that case it is not possible to build a 1MHz clock, because the frequency of the new clock (CLKOUT0) is calculated as 200MHz * (CLKFBOUT_MULT_F / DIVCLK_DIVIDE) / CLKOUT0_DIVIDE_F . And the problem is that CLKOUT0_DIVIDE_F has a permitted range of 1-128. Even using: 

CLKOUT0_DIVIDE_F = 128, 

This leads to 4.687MHz, and it seems that I can then not reach a lower frequency. 

 

Any suggestion? I am thinking on connecting to MMCME2_BASE in cascade to reach the desired frequency, but I do not know is this is a proper solution. It seems too complicated to such an easy task. 

 

Thanks in advance for your help. 

 

José M. Cano

 

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avrumw
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Expert
20,941 Views
Registered: ‎01-23-2009

Jose,

 

What do you need to do with this 1MHz clock?

 

As you have figured out, MMCMs are not great at dealing with very low frequency clocks. So, if possible, it is better to use a higher frequency clock, but use some sort of clock enable to enable logic running at the low rate.

 

So, for example, you could run your entire design at 50MHz, but the part of the design that needs to run at 1MHz, would be desgined to update only on one out of every 50 clocks.

 

This would be done by using a counter on the 50MHz clock that counts down from 49 to 0, and reloads automatically. The "1MHz" flip-flops would only update when this counter equals 0. One way to do this is with the clock enable of the individual flip-flops. Assume "en_clk_1MHz" is the "terminal count" of the 49->0 counter on the 50MHz clock...

 

always @(posedge clk50)
begin
  if (rst...)
  begin
  end
  else if (en_clk_1MHz)
  begin
    // all 1MHz functionality
  end
end

 

Another way to do this is with the BUFGCE or BUFHCE. This can be used to generate a "decimated clock" - a version of the 50MHz clock that is gated so that only 1 out of every 50 pulses gets through. The same counter can be used as the enable to the BUFGCE or BUFHCE - see the attached pictures (in this and the next response).

 

These have the advantage of letting the MMCM run at a "normal" VCO rate to generate the 50MHz clock, but still having the 50MHz and 1MHz clock in phase.

 

The only cases where this won't work is if you are trying to bring this 1MHz "clock" outside the FPGA as a clock - its duty cycle is VERY assymetrical, or if you are using the falling edge of this 1MHz "clock" anywhere - including for an ODDR or IDDR.

 

Avrum

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4 Replies
avrumw
Expert
Expert
20,942 Views
Registered: ‎01-23-2009

Jose,

 

What do you need to do with this 1MHz clock?

 

As you have figured out, MMCMs are not great at dealing with very low frequency clocks. So, if possible, it is better to use a higher frequency clock, but use some sort of clock enable to enable logic running at the low rate.

 

So, for example, you could run your entire design at 50MHz, but the part of the design that needs to run at 1MHz, would be desgined to update only on one out of every 50 clocks.

 

This would be done by using a counter on the 50MHz clock that counts down from 49 to 0, and reloads automatically. The "1MHz" flip-flops would only update when this counter equals 0. One way to do this is with the clock enable of the individual flip-flops. Assume "en_clk_1MHz" is the "terminal count" of the 49->0 counter on the 50MHz clock...

 

always @(posedge clk50)
begin
  if (rst...)
  begin
  end
  else if (en_clk_1MHz)
  begin
    // all 1MHz functionality
  end
end

 

Another way to do this is with the BUFGCE or BUFHCE. This can be used to generate a "decimated clock" - a version of the 50MHz clock that is gated so that only 1 out of every 50 pulses gets through. The same counter can be used as the enable to the BUFGCE or BUFHCE - see the attached pictures (in this and the next response).

 

These have the advantage of letting the MMCM run at a "normal" VCO rate to generate the 50MHz clock, but still having the 50MHz and 1MHz clock in phase.

 

The only cases where this won't work is if you are trying to bring this 1MHz "clock" outside the FPGA as a clock - its duty cycle is VERY assymetrical, or if you are using the falling edge of this 1MHz "clock" anywhere - including for an ODDR or IDDR.

 

Avrum

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avrumw
Expert
Expert
13,005 Views
Registered: ‎01-23-2009

Here is the picture for the BUFHCE.

 

Avrum

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jmcano
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Visitor
12,998 Views
Registered: ‎06-05-2013

Hi avrumw,

 

My intention is to use the 1 MHz clock to sample the data coming from an ADC board. In the future I will use a Mezzanine card, but by now I am trying to use the XADC header from the KC705 evaluation board (2 independent channels sampled at 1 MHz).

 

The 50 MHz clock is used for the internal calculations of my algorithm.   

 

Both of your solutions sounds good. Do you think that they will suit this task?

 

Thanks for your qualified help. 

 

Jose M. Cano

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jmcano
Visitor
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12,970 Views
Registered: ‎06-05-2013

Hi avrumw, 

 

I have finally use a counter to generate my 1MHz clock from system clock (200MHz). I was a bit worried with jitter, but it was not finally a problem. Thanks a lot. 

 

Jose M. cano

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