09-04-2019 03:56 AM
How can I know the maximum Tpd (propogation delay) of the LUT in UltraScale devices? What datasheet/manual/UG should be used in order to figure out these numbers?
What's the longest logical path recommended for 250MHz clock domain in UltraScale devices?
09-04-2019 04:03 AM
I understand your need,
but its not a relavant question.
Reason, FPGAs delays are multiple, wiring delay , lut delay , clock delay ,
In the days of PLD's , yep, a good number, but now,
Your best bet is to do some trial designs of bits, see what speeds you can get.
250 Mhz in an ultrascale is tickling the lower limits,
Also rember, when you do tests ,
look at the routed desing timmng reports, the IO is typicaly the slowest part of a design
the tools run till they meet your timing constraints and stop. No timming constraints , you get what ever spped they found on first build. No optimisatoin without constraints.
09-04-2019 06:45 AM
Actually I want to define how I share the timing between the logic elements and route...
So, I think the thumb rule is giving 50% of timing budget to logic elements and 50% for route.
In order to know how many logic elements (LUTs) I would allow between two flops, I need to know a Tpd of a LUT (worst path).
So, the formula should be simple:
Max # of LUTs between flops = (1/Freq) * 0.5 / (Tpd of LUT)
So, anyway, where can I see the timing parameters of the LUT and other logic elements in the device?
09-04-2019 07:20 AM
Where did you get that rule from,
Ive not heard that for 30 odd years...
this is not your fathers FPGA / CPLD.
routing is very variable, long routes, short routes, inter coloumb routes, et all.
You have to remember, that the tools are going to ripp yor circuit up and layout to meet timming constraints,
doing all sorts of tricks like register duplicatoin and register push back / forward.
then you have the selectoin beteween an F7 , F6 or F4 LUT, and is the routing internal to the slice or external,
or even the Mux or fast carry routes....
There is no number as you ask for,
You get used to each family and its quirks as you gain experiance,
just try a few designs and see, the tools are free .
09-04-2019 07:26 AM
OK, when I synthesize a stand alone module and it meet timing, how can I be sure it will meet the timing after integration it into the whole design?
What thumb rules should be applied to the stand alone module?
09-04-2019 07:30 AM
No rule of thumb needed.
Just good old desing rules.
Number one of which is
All modules, have registered out and ins,
There is no garuntee that any desing will meet an arbirtary timming in any device,
If I have a deivce that is 5% full, a module might run at X, If the deivce is 99 % full,
there is no garuntee that the tools will be able to route the module to run at X,
Thats called design experiance.
09-04-2019 07:34 AM
You wrote: "All modules, have registered out and ins" - so, what is 'ins'? Is ins is instances?
09-04-2019 08:04 AM
I think were getting on to another topic here,
quickly , what design rules are you designing to ?
e.g. try these
These are of much use,
over time, depending upon the companies you work for , and the languages you use,
you will adopt a set of your own design rules which you know work.
The only advise I can give is to read and experiment,
the more you do the more you will ask , the more you will learn.
logic design is a wonderfull life,
09-08-2019 02:49 AM
Anyway, where can I see a Databook (Handbook) for all the LUTs/Cells available in the certain device?
09-08-2019 04:26 AM
The different types of LUTs available in a certain device will be described in the "CLB User Guide" and the "Architecture Libraries Guide". For UltraScale, these guides are UG574 and UG974 and they describe the LUT1, LUT2, LUT3, LUT4, LUT5, and LUT6.
The total number of LUTs in UltraScale devices is shown in DS890.
Surprisingly, there are no electrical specifications for LUTs in the FPGA data sheets.
09-08-2019 05:27 AM
09-08-2019 05:39 AM
So, could some thumb rule be created for a number of logic stages for the stand alone synthesized modules?
The flow is so that each designer do a synthesis of its design as a stands alone unit (a planty cells, no route conjections, so on). But I'd like to create a thumb rule saying the following:
1) synthesize your design as a stands alone unit
2) generate a timing report
3) if you see timing pathes longer than 15 logic stages then brake them in RTL
Does it make sense ?
09-08-2019 05:45 AM - edited 09-08-2019 05:46 AM
Not really ,
Try , first design how your design will be implimented in the hardware
Implement the design
simulate to ensure it meets the design requirements
apply timing constraints
09-08-2019 03:28 PM
But I'd like to create a thumb rule saying the following:
As @drjohnsmith said, there isn't really a rule of thumb - at least not in terms of levels of logic.
However, it is always a good idea to synthesize sub-modules alone to see if your architecture is viable. These should be synthesized in -out_of_context mode (which is the easiest way to get meaningful synthesis and even trial place and route numbers). The only rule of thumb is "If it fails when synthesized alone, it will almost certainly fail when integrated into a design".
In general, unless your design is pretty full and/or working with "scarce" resources (like the RAMBs or DSPs), the speed of a module in isolation should be more or less attainable when it is integrated into a full design - with the possible exception of the paths involving the inputs and outputs (which is why most designers stick to the design rules of "always have your outputs registered, and, if possible, your inputs too). If you have a fairly complex and large sub-module (where most of the complex timing is between the flip-flops of the design) the placement tool is pretty good at keeping this module together and not having interference from other modules...