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Observer
Observer
1,173 Views
Registered: ‎06-03-2015

Maximum Zynq (ZC702) PL Clock

I am trying to configure PL Clock (FCLK_CLK0) to its maximum i.e. 250MHz,I am getting error in Total Negative Slack and Worst Negative Slack. Is there any solution for this?

Timing.png
228MHz.png
240MHz.png
Timing_error.png
HVHF_250MHz.png
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5 Replies
Moderator
Moderator
1,130 Views
Registered: ‎11-09-2015

HI @raseshjd,

I do not think there is any issue going to the maximum frequency of this clock. However you need to make sure the logic clocked by it can support this frequency.

You need to analyse the failing path

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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1,117 Views
Registered: ‎06-21-2017

A number of your failing paths have 3, 4, or 5 levels of logic.  If you are running near the maximum frequency of an FPGA, these will give you trouble.  My suggestion is to add pipeline registers in your failing paths.  This will give the synthesis tool some wiggle room to break up long combinatorial paths and the placer more options in placing registers to reduce routing delays.

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Observer
Observer
1,081 Views
Registered: ‎06-03-2015

Can you please check my attached code and suggest.

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1,057 Views
Registered: ‎06-21-2017

I am a little surprised that this code synthesized.  You should not use rising_edge and falling_edge in the same process.  There are no Double Data Rate (DDR) registers in the core of the FPGA, they are only at the IO ports.  Also, if you are using both edges of the clock, you have only a little more than a 2nS cycle time between edges.  That's awfully fast for Zynq 7000 fabric.  Rewrite your code to only use one clock edge. 

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Voyager
Voyager
373 Views
Registered: ‎08-02-2019

Hi @raseshjd ,

Please mark your thread as solved, because it is clear @bruce_karaffa's reply explains your problem.

Regards,

Saban 

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