11-29-2018 09:09 PM
I am trying to configure PL Clock (FCLK_CLK0) to its maximum i.e. 250MHz,I am getting error in Total Negative Slack and Worst Negative Slack. Is there any solution for this?
11-30-2018 06:17 AM
I do not think there is any issue going to the maximum frequency of this clock. However you need to make sure the logic clocked by it can support this frequency.
You need to analyse the failing path
11-30-2018 10:59 AM
A number of your failing paths have 3, 4, or 5 levels of logic. If you are running near the maximum frequency of an FPGA, these will give you trouble. My suggestion is to add pipeline registers in your failing paths. This will give the synthesis tool some wiggle room to break up long combinatorial paths and the placer more options in placing registers to reduce routing delays.
12-04-2018 05:01 AM
I am a little surprised that this code synthesized. You should not use rising_edge and falling_edge in the same process. There are no Double Data Rate (DDR) registers in the core of the FPGA, they are only at the IO ports. Also, if you are using both edges of the clock, you have only a little more than a 2nS cycle time between edges. That's awfully fast for Zynq 7000 fabric. Rewrite your code to only use one clock edge.
05-17-2020 02:02 PM