Multicycle paths with Vivado and Synplify

[al_gm]

Hi all,

I am using a synthesis flow where I perform synthesis with Synplify Pro, and then perform P&R with Vivado.

I would like to relax constraints for some signals by setting a multicycle path. But I was wondering...

Should I define the constraint in Synplify only? Vivado only? Both?

I believe the correct thing to do would be to mark the registers with a *keep* attribute at synthesis and then constraint the multicycle path only at P&R. What do you think?

Thanks for your feedback!

[nagabhar · Accepted solution]

HI @al_gm

Yes.

As the post P&R timing analysis is what that matters.

Once you import the synthesized netlist from synplify into vivado. You can identify the register-registers path which needs  the multicycle path exceptions and apply them in an xdc file,  which will be used for implementation(P&R).