UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer silvaurus
Observer
388 Views
Registered: ‎10-21-2016

Negative Hold Slack for Custom IP

Jump to solution

Hi!

I'm kinda new to FPGA design. The project I'm working on is a peripheral AXI IP. When I synthesize the IP alone, it reports tons of negative hold time slack. Whilie if I incorporate this IP into block design, sythesis returns all positive slacks.

The constraints I gave for the IP are just (1) defining clock e.g. 10ns (2) input delay for all_inputs 2ns (3) output delay for all_outputs 2ns.

I can pretty much guarantee that the internal logic of my design makes sense, and have been synthesized using Design Compiler and ASIC library.

Could you help me figure out the reason for those negative hold time slacks? Thank you so much!

 

neg_slack.PNG

 

0 Kudos
1 Solution

Accepted Solutions
Visitor peterk
Visitor
297 Views
Registered: ‎04-08-2018

Re: Negative Hold Slack for Custom IP

Jump to solution

If the negative hold slacks are in the same clock domain, then you can ignor them in the synthesis timing report. Implementation normally will fix them.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc

View solution in original post

0 Kudos
3 Replies
Xilinx Employee
Xilinx Employee
323 Views
Registered: ‎01-30-2019

Re: Negative Hold Slack for Custom IP

Jump to solution

Hi @silvaurus 

can you try running report_qor_assesment and report_qor_suggestions from your tcl console.

please have a look at the following to know more about report_qor_suggestions 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug906-vivado-design-analysis.pdf#page=153

--Suraj 

0 Kudos
Xilinx Employee
Xilinx Employee
310 Views
Registered: ‎05-14-2008

Re: Negative Hold Slack for Custom IP

Jump to solution

Can you attatch the timing report file?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
0 Kudos
Visitor peterk
Visitor
298 Views
Registered: ‎04-08-2018

Re: Negative Hold Slack for Custom IP

Jump to solution

If the negative hold slacks are in the same clock domain, then you can ignor them in the synthesis timing report. Implementation normally will fix them.

Peter Kwan, Senior FPGA Engineer
Designlinx Hardware Solution, Inc

View solution in original post

0 Kudos