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Contributor
Contributor
344 Views
Registered: ‎09-24-2016

Net delays and number of nodes

Hello, 

I have a question, just out of curiosity.

After place and route, i have a netA composed of these 5 nodes:

CLBLM_R_X21Y64/CLBLM_L_C
CLBLM_R_X21Y64/CLBLM_LOGIC_OUTS10
INT_R_X21Y64/NR1BEG2
INT_R_X21Y65/IMUX45
CLBLM_R_X21Y65/CLBLM_M_D2

and a netB that goes through these 7 nodes:

CLBLM_R_X21Y64/CLBLM_L_C
CLBLM_R_X21Y64/CLBLM_LOGIC_OUTS10
INT_R_X21Y64/NL1BEG1
INT_R_X21Y65/BYP_ALT1
INT_R_X21Y65/BYP_BOUNCE1
INT_R_X21Y65/IMUX43
CLBLM_R_X21Y65/CLBLM_M_D6

Vivado shows that the delay of netA is 630 ps while the delay of netB is 356ps.

My question is why the delay of netB is smaller that netA ? isn't expected to be larger as it goes through a larger number of nodes?

Thanks

 

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6 Replies
Xilinx Employee
Xilinx Employee
321 Views
Registered: ‎05-14-2008

Re: Net delays and number of nodes

How are the two net's lengths shown in the device window?

Which is longer?

In the timing report, for different analysis, either max delay or min delay is used for calculation.

Are the 630ps and 356ps all for max delay or min, or different?

-vivian

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Contributor
Contributor
287 Views
Registered: ‎09-24-2016

Re: Net delays and number of nodes

Here are NetA and NetB.

They seem to have approximately the same length.

As netB passes through more nodes (more pips) so it should have a larger delay right?

The both reported values are for the max delays


netA.JPGnetB.JPG.

 

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Teacher drjohnsmith
Teacher
282 Views
Registered: ‎07-09-2009

Re: Net delays and number of nodes

Its an eternal question, that has the same answer

    just belive the tools !

It seems that what xilinx show on the plots you have, is a graphic representation, not reality, 

       We assume its due to interlectual property rights or other secrets.

 

 

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Contributor
Contributor
270 Views
Registered: ‎09-24-2016

Re: Net delays and number of nodes

Does this mean that the reported nodes by Vivado are not correct? is it possible that the node in reality passes through another set of nodes? i find this not very convincing ...

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Teacher drjohnsmith
Teacher
259 Views
Registered: ‎07-09-2009

Re: Net delays and number of nodes

Who knows what level of detail they are at,
is a node a single entity, or multiple sub nodes ?
is one route the same speed as the other route , after all routing delays are much larger than gate delays,
Are all routing delays the same ?

The bottom line is the thing that matters is the tools know how to route, which they do, and the reports of delay are reliable, which thay are,

If you want details of the silicon routing,
the previous answers over the years have been on lines that you need to set up an NDA with Xilinx, which is a big deal, for which you need to talk first to your FAE .

The good old days, one could use things like the PIP editor to actually move connections , change luts after you had "compiled" the FPGA, but the things are so complex inside now that is just not possible

for historical interest:
https://www.xilinx.com/support/documentation/sw_manuals/help/iseguide/mergedProjects/fpga_editor/html/fe_c_layvis_toolbar.htm


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Xilinx Employee
Xilinx Employee
199 Views
Registered: ‎05-14-2008

Re: Net delays and number of nodes


@jhgf wrote:

Does this mean that the reported nodes by Vivado are not correct? is it possible that the node in reality passes through another set of nodes? i find this not very convincing ...


Details of the routing resources are confidential.

Just believe the tools. :)

-vivian

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如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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