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Visitor
Visitor
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Registered: ‎06-21-2020

No clock when program the PL of ZCU104

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I am using ZCU104 board for a pure logic development. I do can download the image into the PL by jtag, but it seems the clock not function correctly.

Could any one help? Thanks a lot!

The test code and constrain as following.

 

 

module div_clk(rst, clkp, clkn, div_clk, pbutton, LED);
parameter DIVCNT = 2**20;
input rst;
input clkp;
input clkn;
output div_clk;
input pbutton;
output LED;
 
wire clk;
reg div_clk;
reg [23:0] cnt;
IBUFDS ins_clkbuf(
    .I(clkp),
    .IB(clkn),
    .O(clk));
always @(posedge clk or posedge rst)
  if (rst)
    begin
    cnt <= 0;
    div_clk <= 0;
    end
  else if(cnt == DIVCNT)
    begin
    cnt <= 0;
    div_clk <= ~div_clk;
    end
  else
    cnt <= cnt + 1;
 
   
assign LED = pbutton;

endmodule
 
 
 
 
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clkp]
 
set_property PACKAGE_PIN H11 [get_ports clkp]
set_property IOSTANDARD LVDS [get_ports clkp]
set_property PACKAGE_PIN G11 [get_ports clkn]
set_property IOSTANDARD LVDS [get_ports clkn]
 

set_property PACKAGE_PIN C3 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property PULLDOWN true [get_ports rst]
set_property PACKAGE_PIN B5 [get_ports div_clk]
set_property IOSTANDARD LVCMOS33 [get_ports div_clk]
set_property PACKAGE_PIN A5 [get_ports LED]
set_property IOSTANDARD LVCMOS33 [get_ports LED]
set_property PACKAGE_PIN B3 [get_ports pbutton]
set_property IOSTANDARD LVCMOS33 [get_ports pbutton]
 
 
 
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Xilinx Employee
Xilinx Employee
291 Views
Registered: ‎02-14-2014

Hi @shenglin ,

Yes to correct pin location of 300 MHz clock, we already have CR in place.

Regards,
Ashish
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Highlighted
Visitor
Visitor
304 Views
Registered: ‎06-21-2020

The cause found is error in "ZCU104 Evaluation Board User Guide", see following mismatch between the user guide and schematic

 

um_table3-13.pngzu104_sch.png

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Highlighted
Xilinx Employee
Xilinx Employee
295 Views
Registered: ‎02-14-2014

Hi @shenglin ,

Yes this is bug with user guide and I have reported it through CR.

Correct pins are -

CLK_125_P - F23

CLK_125_N - E23

Regards,
Ashish
----------------------------------------------------------------------------------------------
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Tags (1)
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Highlighted
Visitor
Visitor
293 Views
Registered: ‎06-21-2020
CLK_300_P
CLK_300_N
signals connection is also wrong.
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Highlighted
Xilinx Employee
Xilinx Employee
292 Views
Registered: ‎02-14-2014

Hi @shenglin ,

Yes to correct pin location of 300 MHz clock, we already have CR in place.

Regards,
Ashish
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

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