Hi,
I am confused about the OFFSET IN/OFFSET_OUT constraint.
I want to know if my following understandings about OFFSET IN/OFFSET_OUT are correct？
1.OFFSET_IN before(ucf)/SET_INPUT_DELAY(xdc) defines the time available for data to propagate from the pad and setup at the synchronous element,or defines the time delay from the upstream device to the pad of FPGA device？
2.OFFSET IN timing constraints between 2 FPGAs ，if there is half of clock period skew between the rising edge of the forwarded clock and the data in the upstream one，then the offset value before clk is half of clock period; if there is almost no skew between the rising edge of the forwarded clock and the data in the upstream one, how can I define the offset value before clk?
3.OFFSET IN timing constraints in case of DCM/PLL clock output phase shift. if upstream device's signals are "input input_data ; input clk ". Then the constrain is "NET "input_data OFFSET = IN 5 ns VALID 8 ns BEFORE "clk" RISING" (clock period is 16ns)at first. Then the DCM output clock shifts 90 degrees , so should be the constrain changed to be
"NET "input_data OFFSET = IN 9 ns VALID 4 ns BEFORE "clk" RISING"?
4.Three-state gate : signals from upstream device are "input A , inout [31:0] B ,input clk".
The part of the rtl is "assign B_i = B; assign B = (A) ? 32'bz : B_o".
The constrain is "set_input_delay -clock clk 40ns [get_ports A] set_input_delay -clock clk 40ns [get_ports B] " and the clock period is 80ns. But timing errors occurred. I don't know if the constrains in case of three-state gate is correct ?
5.If I put an OFFSET OUT constraint on the data and valid with a REFERENCE_PIN of the clock,
for example "NET "DATA_o" OFFSET = OUT 5 ns AFTER "clk"; " does the ISE or VIVADO add the delay between clk and DATA_o to meet the 5ns value constrain ?
Clarifications will be greatly appreciated！
