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Participant
Participant
1,143 Views
Registered: ‎06-05-2018

OOC create_clock constraints ignored

I am working on a project which interfaces to DDR3 SDRAM through the MIG. There are several IP's used in this design, as well as several clocks. There are three clocks which come in through the top-level ports (CLK100, CLK400, and CLK162_5). Two clocks are generated with a MMCM and are only used by the DDR3 interface. The DDR3 interface generates a user interface clock (CLK167), which is what the majority of the design runs on.

 

In my XDC file, I have three create_clock constraints:

create_clock -period 2.500 -name CLK400 -waveform {0.000 1.250} [get_ports CLK_400_CLK_P]

create_clock -period 10.000 -name CLK100 -waveform {0.000 5.000} [get_ports S_AXI_ACLK]

create_clock -period 6.154 -name CLK162_5 -waveform {0.000 3.077} [get_ports FMC216_CLK]

 

This XDC file is used in synthesis, implementation, and out of context. I am running synthesis in out of context mode as well. (I am planning on packaging this project as an IP to be used in other projects.) No errors or warnings are generated during synthesis relative to any clocks.

 

When I open the synthesized design and run report_clocks, it doesn't show any clocks in the design. When I run report_clock_networks, it shows the three input clock ports (DDR3_400_CLK_P, FMC216_CLK, and S_AXI_ACLK) as unconstrained. There are no other clocks listed even though there are several generated clocks in the design. I checked to make sure the XDC file was parsed during synthesis, and sure enough, it was. The synthesis report doesn't seem to show any information relative to this issue.

 

I am not sure if I am missing something important with setting OOC timing constraints. Everything I have read seems to agree with the simple create_clock constraints that I wrote, but for some reason, it doesn't seem to be processing these constraints. Any help or suggestions would be greatly appreciated.

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Xilinx Employee
Xilinx Employee
1,097 Views
Registered: ‎01-05-2017

Have you looked in the Vivado log file to see if the create_clock constraints were successfully applied? If the constraints returned errors, they would not halt the Vivado flow and it would continue.

You can also do a write_xdc command to list out what constraints were successfully applied during the run.

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Participant
Participant
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Registered: ‎06-05-2018

I found in the synthesis log:

Parsing XDC File [path_to_file/file_name_ooc.xdc]
Finished Parsing XDC File [path_to_file/file_name_ooc.xdc]

 

No errors or warnings are returned, and this is the only place in the log where this OOC XDC file is mentioned. The only warnings returned from the overall synthesis run are from unused sequential elements, and are expected. 

 

I ran the command: 'write_xdc -constraints all -verbose all_constraints.xdc' and the OOC XDC file was not listed. However, the in-context XDC file and the implementation-only XDC file were listed. I would expect that neither of these would be listed since synthesis was run in out of context mode. 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-05-2017

Do the clocks show up after opt_design and place_design? The IP's might have constraints that only get used in Synthesis or Implementation or both. Constraints can also have a processing order too : EARLY,NORMAL or LATE.

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Participant
Participant
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Registered: ‎06-05-2018

Once I open the implemented design and run report_clock_networks, it shows the three created clocks that were not visible after synthesis. I have the processing order set to EARLY for the OOC XDC file, since it only contains create_clock constraints which are not dependent on any other IP or other constraints. It is possible that this behavior (viewing the clocks after implementation but not after synthesis) is expected, but I was not aware of that. However, I expected that I would be able to see the created clocks after synthesis because the OOC XDC file was included during synthesis.

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