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Voyager
Voyager
607 Views
Registered: ‎04-11-2016

OSERDES timing issue

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Hi,

I am using oserdes in DDR mode at 400 MHz which takes 8 inputs at 100 MHz parallelaly.

 generate if (FPGA_TYPE == 8) begin: G_TX_KINTEXUS
      for (i=0; i <= 1; i = i + 1) begin: G_OSERDES
         OSERDESE3 #(
                     .DATA_WIDTH(8),              // Parallel Data Width (4-8)
                     .INIT(1'b0),                 // Initialization value of the OSERDES flip-flops
                     .IS_CLKDIV_INVERTED(1'b0),   // Optional inversion for CLKDIV
                     .IS_CLK_INVERTED(1'b0),      // Optional inversion for CLK
                     .IS_RST_INVERTED(1'b0),      // Optional inversion for RST
                     .SIM_DEVICE("ULTRASCALE"))   // Set the device version (ULTRASCALE, ULTRASCALE_PLUS,
                                                  // ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2)
         I_OSERDESE3(
                     .OQ(txdata_ser[i]),          // 1-bit output: Serial Output Data
                     .T_OUT(txoe_ser[i]),         // 1-bit output: 3-state control output to IOB
                     .CLK(txclk),                 // 1-bit input: High-speed clock
                     .CLKDIV(txosclkdiv4),          // 1-bit input: Divided Clock
                     .D(txdata_reg_shift[i*8+:8]),      // 8-bit input: Parallel Data Input
                     .RST(reset),                 // 1-bit input: Asynchronous Reset
                     .T(tx_noe));                 // 1-bit input: Tristate input from fabric
        
      end

I used MMCM for vu440 and generated both clocks. It complaining about 2 failing paths which is going to its tristate input T coming out from T_OUT and finally going to output port via OBUFT.

Path 291-3.262332module_ds/tx_oe/Cdata_out_fpga1[1]3.2631.6481.6150.00FB1_uA|I_module_ds.clk_100_pll_derived_clock_CLKIN1 MaxDelay Path 0.000ns -datapath_only 
Path 292-3.032332module_ds/tx_oe/Cdata_out_fpga1[0]3.0321.6861.3460.00FB1_uA|I_module_ds.clk_100_pll_derived_clock_CLKIN1 MaxDelay Path 0.000ns -datapath_only 

 

Max SkewFastOSERDESE3/CLKOSERDESE3/CLKDIV0.3200.417-0.097BITSLICE_RX_TX_X1Y394I_module_ds/I_module_ds_tx/G_TX_KINTEXUS.G_OSERDES[0].I_OSERDESE3/CLK        
Max SkewFastOSERDESE3/CLKOSERDESE3/CLKDIV0.3200.411-0.092BITSLICE_RX_TX_X1Y405I_module_ds_ds/I_module_ds_tx/G_TX_KINTEXUS.G_OSERDES[1].I_OSERDESE3/CLK        

 

and using this constraints didn't help:

set_false_path -from [get_pins I_module_ds/tx_oe/Q]

Any suggestion?

 

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Guide
Guide
519 Views
Registered: ‎01-23-2009

This is a different (and known) issue.

Take a look at this post on managing the clock skew to the OSERDES in UltraScale.

Avrum

View solution in original post

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Xilinx Employee
Xilinx Employee
596 Views
Registered: ‎05-14-2008

Not sure what paths they are.

Information not enough.

Would you post your complete timing report?

And can you show us the schematic of the related timing paths?

-vivian

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Voyager
Voyager
588 Views
Registered: ‎04-11-2016

     
Summary     
Name Path 291    
Slack -3.263ns    
Source I_module_ds/tx_oe/C   (rising edge-triggered cell FDCE clocked by FB1_uA|I_module_ds.clk_100_pll_derived_clock_CLKIN1  {rise@0.000ns fall@5.000ns period=10.000ns})    
Destination data_out_fpga1[1]       
Path Group **default**    
Path Type Max at Slow Process Corner    
Requirement 0.000ns (MaxDelay Path 0.000ns)    
Data Path Delay 3.263ns (logic 1.648ns (50.499%)  route 1.615ns (49.501%))    
Logic Levels 3  (LUT1=1 OBUFT=1 OSERDESE3=1)    
Output Delay 0.000ns    
Timing Exception MaxDelay Path 0.000ns -datapath_only    
     
Data Path     
Delay Type Incr (ns) Path (ns) Location Netlist Resource(s) Partition
 (r) 0.000 0.000 Site: SLICE_X297Y455 I_module_ds/tx_oe/C 
FDCE (Prop_AFF_SLICEL_C_Q) (r) 0.140 0.140 Site: SLICE_X297Y455 I_module_ds/tx_oe/Q 
net (fo=2, routed) 0.082 0.222  I_module_ds/tx_oe 
   Site: SLICE_X297Y455 I_module_ds/tx_oe_RNI9U1D.O/I0 
LUT1 (Prop_B6LUT_SLICEL_I0_O) (f) 0.053 0.275 Site: SLICE_X297Y455 I_module_ds/tx_oe_RNI9U1D.O/O 
net (fo=2, routed) 0.767 1.042  I_module_ds/I_module_ds_tx/tx_oe_i_0 
   Site: BITSLICE_RX_TX_X1Y405 I_modulen_ds/I_module_ds_tx/G_TX_KINTEXUS.G_OSERDES[1].I_OSERDESE3/T 
OSERDESE3 (Prop_OSERDES_BITSLICE_COMPONENT_RX_TX_T_T_OUT) (f) 0.450 1.492 Site: BITSLICE_RX_TX_X1Y405 I_module_ds/I_module_ds_tx/G_TX_KINTEXUS.G_OSERDES[1].I_OSERDESE3/T_OUT 
net (fo=1, routed) 0.766 2.258  I_module_ds/I_module_ds_tx/txoe_ser[1] 
   Site: AV31 I_module_ds/I_module_ds_tx/G_txdata[1].G_obuft.I_OBUFT_txdata/T 
OBUFT (TriStatE_OUTBUF_HPIOB_T_O) (r) 1.005 3.263 Site: AV31 I_module_ds/I_module_ds_tx/G_txdata[1].G_obuft.I_OBUFT_txdata/O 
net (fo=0) 0.000 3.263  data_out_fpga1[1] 
   Site: AV31 data_out_fpga1[1] 
Arrival Time  3.263   
     
Destination Clock Path     
Delay Type Incr (ns) Path (ns) Location Netlist Resource(s) Partition
max delay 0.000 0.000   
output delay -0.000 0.000   
Required Time  0.000   

 

serdes_out_2.jpg
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Highlighted
Guide
Guide
551 Views
Registered: ‎01-23-2009

The problem is with your constraints. Somewhere in the design you have a command that looks like

set_max_delay -datapath_only 0 <some path enumeration>

This includes the path that ends at the primary output of your FPGA. A set_max_delay 0 is essentially impossible to meet. It is also really unusual to have a set_max_delay -datapath_only to a primary output of the FPGA.

Unless you have "correct" constraints, the timing analysis is meaningless - and this is clearly not a correct constraint...

Avrum

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Voyager
Voyager
528 Views
Registered: ‎04-11-2016

hi @avrumw 

i could manage to remove

set_max_delay -datapath_only 0 <some path enumeration>

but I still have pulse width skew problem which i also mentioned above.

see attachments.

serdes_out_3.jpg
serdes_out_4.jpg
serdes_out_5.jpg
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Highlighted
Guide
Guide
520 Views
Registered: ‎01-23-2009

This is a different (and known) issue.

Take a look at this post on managing the clock skew to the OSERDES in UltraScale.

Avrum

View solution in original post

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