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Contributor
Contributor
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Registered: ‎03-03-2017

Optimal circuit design and time constrains for PS SPI

I have activated the PS SPI on a Xilinx Zynq UltraScale via EMIO port. I have also followed the recommendations provided by @avrumw in this post, so that output/input data is buffered by the SPI clock in the output port, and the clock itself is first buffered using a BUFG and later an ODDR is used to send it to the output port:

1.png

In the block design “design 1”, the outputs coming from the PS SPI go directly to an output. The SPI-clock frequency is 12.5 MHz and the time constraints, considering tsu = 25 ns, th = 25 ns and a propagation delay of 0.25 ns, are:

 

set fwclk        SPI_CLK;          # forwarded clock name (generated using create_generated_clock at output clock port)        
set tsu          25.000;           # destination device setup time requirement
set thd          25.000;           # destination device hold time requirement
set trce_dly_max 0.250;            # maximum board trace delay
set trce_dly_min 0.250;            # minimum board trace delay
set output_ports SCLK;             # list of output ports

# Create clock
create_clock -period 80.000 -name $fwclk [get_pins design_1_wrapper_i/design_1_i/zynq_ultra_ps_e_0/emio_spi0_sclk_o]

# Output Delay Constraints
set_output_delay -clock $fwclk -max [expr $trce_dly_max + $tsu] [get_ports $output_ports];
set_output_delay -clock $fwclk -min [expr $trce_dly_min - $thd] [get_ports $output_ports];

I was not expecting having much problems at this frequency, but after running implementation, it failed timing:

15.PNG

In particular:

 


2.png

According to the post commented before, this should be corrected by using an output delay (ODELAY) or inverting the outgoing clk. However, I suspect I’m not doing this correctly, since the path between the clk output from the PS and the BUFG is very long (in green the path for the clk from the PS output to the BUFG, and in yellow the path for the MOSI from the PS output to the output register):

 

3.png

Should I improve this design somehow or can I continue fighting with ODELAYs nad/or polarities in order to avoid time violations?

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Contributor
Contributor
423 Views
Registered: ‎03-03-2017

Re: Optimal circuit design and time constrains for PS SPI

Please, can anyone provide some clarification on this? 

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