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Adventurer
Adventurer
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Registered: ‎01-20-2017

Output signals defined as false paths showing up in Output Delays page of Timing Constraints Wizard

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I have a number of output signals in my design that are not critical (like signals driving LEDs or reset signals).  I have therefore defined them as false paths using a constraints like

set_false_path -from [get_cells -hierarchical *leds_cs_reg*]

However, after running synthesis with these constraints defined, I run the Timing Constraints Wizard.  And when I get to the Output Delays page, all of these signals that are defined as false paths still show up in the window as 'Recommended Constraints'.

Why is that?

 

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Registered: ‎01-22-2015

@efpkopin 

     Why is that?
I understand how this can be annoying.  However, a timing path that starts on an FPGA register (eg. leds_cs_reg) cannot actually end on an FPGA port.  Strictly speaking, a timing path can start on an FPGA register, go through an FPGA port, and end on a register located outside the FPGA.  However, the Vivado tools don’t know there is a register located outside the FPGA until you write the set_output_delay constraint for the port.   So, without the set_output_delay constraint, there is no path to identify as a "false path".

I suggest keeping your set_false_path constraint as-is and let the Constraints Wizard put meaningless set_output_delay constraints on the port connected to leds_cs_reg.

The Constraints Wizard can be annoying in other ways too.  A frequent complaint is that it makes a mess of your tidy and well-organized XDC file.  In some versions of Vivado, the Constraints Wizard is actually destructive, stripping off and throwing away in-line comments and Tcl commands that you wrote.  You might want to read <this> post to see how new_user avoids these problems.  

Cheers,
Mark

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409 Views
Registered: ‎01-22-2015

@efpkopin 

     Why is that?
I understand how this can be annoying.  However, a timing path that starts on an FPGA register (eg. leds_cs_reg) cannot actually end on an FPGA port.  Strictly speaking, a timing path can start on an FPGA register, go through an FPGA port, and end on a register located outside the FPGA.  However, the Vivado tools don’t know there is a register located outside the FPGA until you write the set_output_delay constraint for the port.   So, without the set_output_delay constraint, there is no path to identify as a "false path".

I suggest keeping your set_false_path constraint as-is and let the Constraints Wizard put meaningless set_output_delay constraints on the port connected to leds_cs_reg.

The Constraints Wizard can be annoying in other ways too.  A frequent complaint is that it makes a mess of your tidy and well-organized XDC file.  In some versions of Vivado, the Constraints Wizard is actually destructive, stripping off and throwing away in-line comments and Tcl commands that you wrote.  You might want to read <this> post to see how new_user avoids these problems.  

Cheers,
Mark

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Adventurer
Adventurer
378 Views
Registered: ‎01-20-2017
@markg@prosensing.com - yes I have experienced the stripping out of in-line comments in my xdc files by the tools (the hard way!) These days, if I have a comment I want to include around a constraint - I give it its own line! Thanks for the response.
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