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dharpeer
Adventurer
Adventurer
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Registered: ‎11-24-2020

PVT - fast and slow corners

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Hi,

Vivado allows to disable the slow corner and perform analysis only for the fast corner and wise versa. However in default mode both corners are considered. What is the impact of this? What are the tradeoffs?

Thanks

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avrumw
Expert
Expert
385 Views
Registered: ‎01-23-2009

The ability to modify the default timing corners is mostly legacy - Synopsys, which created SDC, on which XDC is closely based, allowed for this feature.

The default right now is that four (really eight) checks are done on each path

  • Setup at slow process corner
  • Hold at slow process corner
  • Setup at fast process corner
  • Hold at fast process corner

(there are actually two done at each combination above - for rising data edge and falling data edge, but in the FPGA all edges are symmetrical so this doesn't carry any additional information).

In most internal paths you generally see two of these as being worse than the other two - setup at slow process corner and hold at fast process corner. The timing engine configuration is flexible enough to allow you to use only these two and turn off the other two. The idea would be that your synthesis and place and route runs would be faster.

But DON'T! There are a class of paths that are worst at the other corners. If you turn off the other timing corners you won't be synthesizing/implementing at with the most pessimistic assumptions and you can get situations where the tool says your design passes timing, but it will fail in real life.

While you can do all kinds of fancy things (turn them off at synthesis and implementation to get some speed, then turn them back on for analysis and then do another optimization step if required), almost no one does this. I don't know what the benefits in terms of run time would be, but there is way too much opportunity for error.

So (and others can chime in if they know otherwise) I think almost no one does this, and it is not recommended.

Avrum

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avrumw
Expert
Expert
386 Views
Registered: ‎01-23-2009

The ability to modify the default timing corners is mostly legacy - Synopsys, which created SDC, on which XDC is closely based, allowed for this feature.

The default right now is that four (really eight) checks are done on each path

  • Setup at slow process corner
  • Hold at slow process corner
  • Setup at fast process corner
  • Hold at fast process corner

(there are actually two done at each combination above - for rising data edge and falling data edge, but in the FPGA all edges are symmetrical so this doesn't carry any additional information).

In most internal paths you generally see two of these as being worse than the other two - setup at slow process corner and hold at fast process corner. The timing engine configuration is flexible enough to allow you to use only these two and turn off the other two. The idea would be that your synthesis and place and route runs would be faster.

But DON'T! There are a class of paths that are worst at the other corners. If you turn off the other timing corners you won't be synthesizing/implementing at with the most pessimistic assumptions and you can get situations where the tool says your design passes timing, but it will fail in real life.

While you can do all kinds of fancy things (turn them off at synthesis and implementation to get some speed, then turn them back on for analysis and then do another optimization step if required), almost no one does this. I don't know what the benefits in terms of run time would be, but there is way too much opportunity for error.

So (and others can chime in if they know otherwise) I think almost no one does this, and it is not recommended.

Avrum

View solution in original post