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Explorer
Explorer
441 Views
Registered: ‎04-12-2012

Phase shift between 2 MMCMs

Hello,

I'm having trouble understanding Avrum's response to this thread:

https://forums.xilinx.com/t5/Other-FPGA-Architectures/Undesirable-Phase-shifts-between-two-similar-MMCMs/m-p/923272#M31073

Consider a scenario that obeys the following conditions:

1. Clock_X of a 100MHz frequency is fed from an input pin to 2 different MMCMs.

2. Both MMCMs are configure to output 200 MHz from the 100 MHz.

3. Both MMCMs are configured to have a ZERO phase shift between the 200 MHz output and Clock X. I.E: if we where able to magically measure them inside the FPGA and show them on an osciloscope screen - each MMCM's output will be EXACLY on top of its input . 

 

By simple logic, if condition #3 takes effect correctly - I don't see how the outputs of both MMCMs can be out of phase with each other.   

What am I missing ?

 

7 Replies
430 Views
Registered: ‎09-17-2018

Re: Phase shift between 2 MMCMs

 
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426 Views
Registered: ‎09-17-2018

Re: Phase shift between 2 MMCMs

The rising edge of the 100 MHz coincides with only one rising edge of 200 MHz,

So, there is a even/odd situation, there is no guarantee both lock, one may be early with respect to the other.  The two outputs are in phase, but one may be 360 degrees late w.r.t. the other ....

l.e.o.

 

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Explorer
Explorer
419 Views
Registered: ‎04-12-2012

Re: Phase shift between 2 MMCMs

The two outputs are in phase, but one may be 360 degrees late w.r.t. the other ....

With this I can agree. But this isn't what Avrum says.

As far as I understand - the outputs can have any phase between between them. Quote:

"which can result in them having a phase difference in increments of one VCO period"

Please note he didn't say "one VCO period" - but "increments of..." I.E: n * VCO_period.

 

 

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365 Views
Registered: ‎09-17-2018

Re: Phase shift between 2 MMCMs

I do not agree,

The 2X clock function of the DCM uses the rising edge of the clock and creates a 2x frequency perfectly aligned to that edge (within 100ps error).  Use of IBUFG to get to DCM, and BUFG to feedback the CLK0, and BUFG to distribute 2X clock should have the two separate device 2X clocks looking close (200 ps error, plus whatever pcb layout mis-match, plus any mismatc in process (speed) between the two).

l.e.o.

 

Explorer
Explorer
360 Views
Registered: ‎04-12-2012

Re: Phase shift between 2 MMCMs

"I do not agree"

With Avrumw ?

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297 Views
Registered: ‎01-22-2015

Re: Phase shift between 2 MMCMs

@shaikon 

By simple logic, if condition #3 takes effect correctly - I don't see how the outputs of both MMCMs can be out of phase with each other.  
With your statement of conditions, the outputs of the two MMCMs will be in-phase.  Implied by your condition-3 is that the MMCMs have been configured for “Phase-Alignment” as described on about page-35 of PG065.  When this Phase Alignment feature is turned OFF, then (I think) you have the description of things given by Avrum in the post that you referenced.

It is odd that neither UG472 nor UG572 say that Phase-Alignment is an optional feature of the MMCM - but, PG065 makes this clear.

Also, when MMCM Phase-Alignment is turned ON, some (perhaps unexpected) results can occur.  Suppose, CLKIN1=100MHz=CLKOUT1 for MMCM1 and CLKIN2=300MHz=CLKOUT2 for MMCM2.  Further, suppose that CLKIN1 and CLKIN2 have 0ns latency difference (ie. rising edges of CLKIN1 always correspond with rising edges of CLKIN2).  Then, because of the variable-time-to-lock for each MMCM, power-up of the FPGA may result in CLKOUT1 and CLKOUT2 having either 0ns or 3.33ns or 6.66ns latency difference.  That is, although CLKIN1 and CLKIN2 may be synchronous, we must consider CLKOUT1 and CLKOUT2 to be mesochronous (ie. known frequency but unknown phase).

The 7-Series BUFR_DIV (UG472) with divide>1 is another way to create (perhaps unexpected) mesochronous clocks from synchronous clocks.  To prevent this, a special BUFR_DIV alignment procedure is needed (see Appendix-A of UG472).  I suspect that a similar alignment procedure is needed for the UltraScale BUFGCE_DIV with divide>1 – although, I cannot find mention of it in UG572.

Mark

Explorer
Explorer
278 Views
Registered: ‎04-12-2012

Re: Phase shift between 2 MMCMs

power-up of the FPGA may result in CLKOUT1 and CLKOUT2 having either 0ns or 3.33ns or 6.66ns latency 

With this I agree.

But Avrumw in his post mentioned that the phase missalignement can have misaligned phase at ANY increment of VCO period.

And this I don't understand.

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