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Participant
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Registered: ‎10-07-2016

Processor System Register Latch pin with no clock

Hi,

 

I'm having trouble figuring out if its safe to ignore this message or what I should do about it.

 

"Register/Latch pins with no clock driven by root clock pin: tx_path_i/zynq_ultra_ps_e_0/U0/PS8_i/EMIOSPI0SCLKO (1)"

 

I'm using a Zync Ultrascale+ and have of the processor system SPI blocks on EMIO that I'm routing to PL pins.

 

Can I ignore these?

Given these pins are sourced in the processor system, I don't think I can write a constraint to fix the problem?

What would a false path constraint look like for this?


Thanks,

 

Chuck_S

 

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