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whisper
Visitor
Visitor
10,262 Views
Registered: ‎04-07-2014

Question of delay time on same hardware description

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未命名.JPG

Timing Detail LA.PNG

 

 

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CL.JPG

CL_delay.JPG

 

Here is the question

Why the same hardward description get the different delay?

I just changed  prefix to the lower case but why

I was used the Xilinx ISE 10.1and get the Synthesis report of Design summary

I confused for a long time

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markus.offergeld
Explorer
Explorer
17,605 Views
Registered: ‎02-28-2011

Hi,

 

by changing the name you will also change the order of snythesis/mapping and you will end up with a different map/place and route. Note that you not only changed the case but the name of the module itself.

Let asume the order is alphabetical and you have other modules/blocks in your system. If you module comes first it will use FPGA placement at site X. If your module comes second however, then site X might have been already used -> your module will use a different placement -> routing and timing becomes different.

This is normal and there is no need to worry about this unless your final timing report is failing

 

Regards Markus

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viviany
Xilinx Employee
Xilinx Employee
10,250 Views
Registered: ‎05-14-2008

First, although the two sets of code are only of different case, they are DIFFERENT CODES. It won't suprise me that they produce different synthesis result - saying netlists and Synthesis timing results. 

 

Second, the two delays in your examples are similar - 9.157 and 9.882. This difference between the two at the Synthesis stage is reasonable as the Synthesis timing analysis is just estimated. 

 

You don't need to struggle with the XST synthesis timing analysis result. Go straight to the post-MAP or post-PAR timing and those are more meaningful for you to do timing closure.

 

-Vivian

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markus.offergeld
Explorer
Explorer
17,606 Views
Registered: ‎02-28-2011

Hi,

 

by changing the name you will also change the order of snythesis/mapping and you will end up with a different map/place and route. Note that you not only changed the case but the name of the module itself.

Let asume the order is alphabetical and you have other modules/blocks in your system. If you module comes first it will use FPGA placement at site X. If your module comes second however, then site X might have been already used -> your module will use a different placement -> routing and timing becomes different.

This is normal and there is no need to worry about this unless your final timing report is failing

 

Regards Markus

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hj
Moderator
Moderator
10,214 Views
Registered: ‎06-05-2013
Could you please compare the post implementation timing in both the cases?

Check the difference. Since exact timing with routing delays can be observed after implentation.

Regards,
Harry
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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