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Visitor dm_wang
Visitor
402 Views
Registered: ‎08-02-2018

RLOC on DSP48E2 problem

hi all,  i am working on a high speed dsp project. need to rloc the dsp place. 

i have made 4 pblock at top. no overlap between each other.  rloc some sub-module DSP site like this:

(* RPM_GRID = "GRID" *)
 
(* RLOC = "X0Y0" , HU_SET = "uset0" *) dsp_module

(* RLOC = "X0Y10", HU_SET = "uset0" *) dsp_module
(* RLOC = "X0Y20", HU_SET = "uset0" *) dsp_module
(* RLOC = "X0Y30", HU_SET = "uset0" *) dsp_module

 

tming meet while separately routiing each pblcok .but route whole 4 timing get worst. compare result, i thinl DSP loc is the problem. 

 

 

btw, not direct inst dsp primitive and dsp_module contain other logic.

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1 Reply
Explorer
Explorer
226 Views
Registered: ‎07-18-2018

Re: RLOC on DSP48E2 problem

Hi dm_wang,

    If you are still having this problem, could you provide an example design that shows the problem?

I am not sure I understand the steps you are taking? Are you LOC'ing DSP's inside 4 pblocks? What do the paths look like when you route them individually vs all together?

Does the router or tool provide any messages? Can you after a failed route, select the failed nets, un-route, and have the tool successfully route them one by one?

 

If you resolved the problem, could you share what you discovered? It might be helpful to other people who might try to do something similar themselves.

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