02-27-2019 04:10 PM
I have implemented a simple design using vivado hls and integrated the ip with the Xilly bus ip.
I am able to run synthesis and implementation successfully. But I am getting error in the bit stream generation.
I have attached the screenshot of the error.
Please let me know how to resolve this issue.
02-27-2019 05:18 PM
Hi, @vivek ,
Please add the create_clock contraints on the reported ODIV2 pin.
02-28-2019 10:25 AM
Hi @hongh ,
Thank you for your response.
I added the following command in the xdc file - create_clock -name sys_clk -period 10 [get_ports blockdesign_ins/xillybus_bundled_0/inst/pcieclk_ibuf/ODIV2]
But still, I am facing the same issue. I have attached the xdc file in .txt file
Please let me know how to resolve the issue. I also went through the schematic and found that the ODIV2 pin is connected to the sys clk!
02-28-2019 03:22 PM
The command you used is not correct (and I question the solution as well).
blockdesign_ins/xillybus_bundled_0/inst/pcieclk_ibuf/ODIV2 is not a "port" - a port is only at the top of the design (it is a primary input or output of the design). Therefore, your [get_ports ...] returned a null list, which didn't accomplish anything. I don't know what ODIV2 is, but it is most likely a pin not a port.
But even with that, it is almost always incorrect to define a primary clock (with a create_clock) inside the FPGA. How did this clock get here? Since FPGAs can't generate clocks "from nothing" by definition any clock is derived from some primary clock applied to the ports of the FPGA (which is why a "create_clock" on an internal pin is almost never used). The only exception is the TXOUTCLK and RXOUTCLK of a GT (at least in 7 series); while, in reality, these clocks are derived from the reference clock applied to the GT, the tools cannot propagate the clocks through the GT automatically (as they do to other clock modifying blocks; the MMCM, PLL, BUFR).
In rare cases, it is necessary to have an manual create_generated_clock on an internal pin, but this would be used when a clock is being generated by a non clock modifying block, like a BUFGE, BUFHCE, or an ODDR on an output pin (or from a flip-flop, but this is not recommended practice).
So, before we go and create some clock on an unknown internal node (just because there isn't one there already), we need to figure out why there isn't one there. In a properly built system with proper "create_clock" commands on the primary clock input ports, we should not end up with a "no_clocks" warning. This is especially true of something made with IP since all IP comes with its own constraints which will create any required generated clocks (and in the case of the clocking wizard, even primary clocks). But in your design, you get this warning. This is an indication that there is "something wrong" with your design - maybe a net is not properly connected somewhere in the hierarchy or there is something else illegal about how your design is clocked. You need to figure out what that is and fix it (rather than just throw an additional constraint in there).
02-28-2019 03:49 PM
Yes, you are correct.
I just checked my simulation results and found pcie_clk in Z state.
I have attached the screenshot of the simulation and the block design.
I am assuming something wrong with the clock generation!
02-28-2019 03:55 PM
thanks for the response.
I was able to generate bitstream this time. I don't know how it got fixed.
I just made a new project and added the xillybus ip and the waveform ip.
But, I am getting high Z state in the PCIe clk and PCIERX. Any ideas?
I also wrote a simple host application to write some data to fpga and receive data back from the fpga.
I am able to compile the program successfully but I do not get any output when I execute the program!