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Visitor
Visitor
7,145 Views
Registered: ‎10-14-2015

Router estimated timing not met. - Neagtive WNS and TNS

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Hello, 

 

I am working a 3D rendering project on Kintex 7 board and I face a problem with timing.
After I run Implementation I see this error.

 

Screenshot_1.png

 

I can generate the bistream ans test it but it seems that it is static. I mean that something is going wrong with the clock.

 

Also, i saw that WNS and TNS are negative .

Screenshot_4.png    Screenshot_5.png

 

Kintex7 Uses differential clock input 200MHz and for my implementation I need two clocks, one for I2C (100MHz) and one for the rest implementation (150MHz). I have done this using IP Clocking Wizard. In the XDC i use this for clock.

 

Screenshot_6.png

 

I have ran simulation and all work fine. So I think that the problem is with clock.

I would appreciate any response. Thanks in advance.

-Fotis

 

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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Guide
Guide
12,351 Views
Registered: ‎01-23-2009

The problem is with your architecture.

 

The first failing path goes combinatorially through two DSP48E1 cells. While I can't tell the operation itself, I suspect it is doing a multiply or multiply/accumulate of a large value (more than 25x18 multiply). After the DSP48 cells, there are still 6 LUTs of additional processing before the result hits a flip-flop.

 

You are trying to run this at 6.66ns. This path has way too much logic to run at this speed... You need to re-evaluate your architecture and add at least one (I would highly suggest more) pipelining to this path. Without changing your RTL code, it is unlikely that you will get this design to meet timing.

 

Avrum

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Xilinx Employee
Xilinx Employee
7,137 Views
Registered: ‎05-07-2015

HI @fpegios

 

From the timing report, obviously your desing has many setup timing violations(5599).

Always ensure the performance of your design from Post-implementation timing simulation (not just behavioural simulation) and only then proceed to generate the bitstream.

Thanks
Bharath
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Visitor
Visitor
7,134 Views
Registered: ‎10-14-2015

Hi Bharath,

 

Thanks for the quick reply. How can I avoid that problem? I s there a certain way?

 

Thanks

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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Visitor
Visitor
7,125 Views
Registered: ‎10-14-2015

@nagabhar

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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Xilinx Employee
Xilinx Employee
7,117 Views
Registered: ‎05-07-2015

HI @fpegios

Can you please share your timing report?

Also please confirm that your design is indeed not working as expected in post_implementation timing simulation itself.

Thanks
Bharath
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Visitor
Visitor
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Registered: ‎10-14-2015

Hi @nagabhar

 

Here is the timing report.

 

Thanks

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
0 Kudos
Highlighted
Guide
Guide
12,352 Views
Registered: ‎01-23-2009

The problem is with your architecture.

 

The first failing path goes combinatorially through two DSP48E1 cells. While I can't tell the operation itself, I suspect it is doing a multiply or multiply/accumulate of a large value (more than 25x18 multiply). After the DSP48 cells, there are still 6 LUTs of additional processing before the result hits a flip-flop.

 

You are trying to run this at 6.66ns. This path has way too much logic to run at this speed... You need to re-evaluate your architecture and add at least one (I would highly suggest more) pipelining to this path. Without changing your RTL code, it is unlikely that you will get this design to meet timing.

 

Avrum

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Visitor
Visitor
7,063 Views
Registered: ‎10-14-2015

@avrumw @nagabhar

 

Thanks, I have figured out that problem! How can I run post place and route simulation on Vivado?

 

Fotis

 

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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Moderator
Moderator
7,054 Views
Registered: ‎07-01-2015

Hi @fpegios,

 

Please give kudo(star on the left) to answer that helped you to find solution.

 

For Post place and route simulation please follow the following steps.

1. Implement Design

2. Navigate to Flow Navigator->Simulation

3. Click on Run Simulation. You will see the option for Post Implementation Functional as well as timing simulation.

 

Attaching a snapshot for your reference.

 

Thanks,
Arpan

 

Thanks,
Arpan
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Visitor
Visitor
7,048 Views
Registered: ‎10-14-2015

Hi @arpansur

 

There is no flow navigator option. I use Vivado 2014.Screenshot_3.png

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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Moderator
Moderator
5,758 Views
Registered: ‎07-01-2015

Hi @fpegios,

 

I mean Flow Navigator. See the screenshot.

After implementation complates. Go to simulation. See the screenshot attached in my previous post.

 

Thanks,
Arpan

Thanks,
Arpan
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Moderator
Moderator
5,752 Views
Registered: ‎07-01-2015

Hi @fpegios,

 

Are you able to proceed with post-implementation simulation now?

Please let us know if you are facing any difficulty in understanding the flow.

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor
Visitor
5,748 Views
Registered: ‎10-14-2015

@arpansur

 

I have run the post implementation functional simulation but it too slow. If I face any difficulty with that I will post again.

 

Thanks a lot!!

 

Fotis

--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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Moderator
Moderator
5,734 Views
Registered: ‎07-01-2015

Hi @fpegios,

 

Please start a new thread in Simulation and Verification Community if you are getting any simulation issue to target the right audience.

 

Thanks,
Arpan

Thanks,
Arpan
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Visitor
Visitor
5,732 Views
Registered: ‎10-14-2015
Alright @arpansur. Thanks for the help!

Fotis
--
Fotis Pegios
Senior Undergraduate Student
Department of Electronics and Computer Engineering
Technical University of Crete, Greece

http://fpegios.blogspot.gr/
fpegios92@gmail.com
Tel.: (0030) 694 464 7289
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