cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
jonmccallum
Participant
Participant
11,017 Views
Registered: ‎12-10-2013

Routing timing driven Algorithm

Hello,

 

I am currently workiing on porting an rtl design to an ARTIX-7 Board.

 

When running the route_design option with -no_timing_driven it will turn off the routing algorithm to ignore constraints. Does this necessarily mean that the design can no meet timing constraints? Or to meet timing constraints do you have to run route_design without the option.

 

This seems a little ambiquous to me. 

0 Kudos
4 Replies
hj
Moderator
Moderator
11,004 Views
Registered: ‎06-05-2013



If you select no timing driven then it will ignore timing driven routing. So it does not mean that design cannot meet timing.

Vivado is a timing driven tool. Due to the issue Vivado 2013.3 please follow the below tcl commands after synthesis.
opt_design
power_opt_design
place design
phys_opt_design
route_design

After route design you can run check_timing to check the timing results.

After two days you can use 2013.4 as it will be released without the use of TCL command.


Thanks

-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
jonmccallum
Participant
Participant
10,994 Views
Registered: ‎12-10-2013

Should I leave out the phys_opt_design If I do not want to go through resynthesis?

0 Kudos
hj
Moderator
Moderator
10,985 Views
Registered: ‎06-05-2013



you have to perform above steps after synthesis.

 

For implementation you must run

opt_design

place_design


route_design

You can ignore phy_opt_design if you want.



Thanks

-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
sampatd
Scholar
Scholar
10,970 Views
Registered: ‎09-05-2011

As mentioned in the previous post, phys_opt_design is optional. If you have any negative-slack paths in the design then this option does timing driven optimization on them. You may choose to not do this.

You can use the argument "-no_timing_driven" in either place_design or route_design. Depending on where you use the command will ignore the timing constraints in either place or route respectively.
0 Kudos