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maximecadel
Visitor
Visitor
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Registered: ‎06-02-2016

Serialisation 7:1 - HOLD VIOLATION on the RST pin with requirement 0ns

Hi guys,

I'm currently setting a serialiser module on Zynq Device - Z7045 -3 speedgrade, and I get timing error on OSERDESE2 Reset pin. 

 

 display_schematic.JPG

 

The module serializes data in SDR mode 7x49.5Mhz (to 346.5Mhz).

 


 

I have used XAPP585 in SDR mode as the example:

 

xapp_585.png

My output clocks are generated (like the xapp585) by a MMCM (same result with a PLL), driven by BUFG for Pixel-Clock (Clock_divide-49.5Mhz) and BUFG for High-SpeedClock (SerDes clock 346.5Mhz).

 

The reset signal is generated by the inverted lock signal of the MMCM ,  then re-clock by the CLK_DIV signal as UG768 (the  Xilinx 7 Series FPGA Libraries Guide for HDL Designs) said:

“the user is only required to provide a reset pulse to the RST input that meets timing on the CLKDIV frequency domain (synchronous to CLKDIV).”

 


 

 

But i get this result after synthesis in static timing analyzes: a negative slack on hold, i get logic delay with a requirement of 0.0ns.

 

hold_negative_slack.JPG

 

If someone can help me.

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muravin
Scholar
Scholar
6,366 Views
Registered: ‎11-21-2013

Max,

If you don't care about the reset, put a set_false_path on it. This is what we do, and we don't have any complaints or issues.

BR
Vlad
Vladislav Muravin
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