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Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

Scholar
Posts: 1,166
Registered: ‎09-16-2009

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

[ Edited ]

 

That AR is a rather awful excuse for why the attribute doesn't work. The attribute "can only be applied on cells"?  What is this 1990?  We're designing RTL here, folks.  Not schematic capture, instatiating primitives.

 

The XDC workaround is klunky - to difficult to manage and insure the attribute gets applied everywhere.  I suppose with a scoped XDC I might be able to get things to work, but the attribute was the best solution.    Xilinx should fix this.

 

Regards,

 

Mark

 

Advisor
Posts: 566
Registered: ‎01-22-2015

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

drjohnsmith:

 

Based on your last posts, I put together the following method for setting the ASYNC_REG property of registers used in the 2FF synchronizer:

 

1) Created a VHDL component to implement the 2FF synchronizer and called it SYNC_2FF.vhd. 

2) Inside SYNC_2FF.vhd, I used the "2FF:" process shown in my original post.

3) Inside SYNC_2FF.vhd, I removed all the attribute lines (ie. the lines that I was previously using to set ASYNC_REG).

4) Instantiated SYNC_2FF in my project as needed

5) Ensured that signal names, sig_meta and sigb, used in SYNC_2FF are not used elsewhere in the project <<important

6) Added the following constraints to the XDC file:

    set_property ASYNC_REG TRUE [get_cells -hierarchical *sigb_reg]

    set_property ASYNC_REG TRUE [get_cells -hierarchical *sig_meta_reg]

 

After running synthesis and implementation, I opened the implemented design and inspected all my instances (24ea) of SYNC_2FF.  I found that the sigb and sig_meta registers were always located in the same slice - just what is needed!

 

Note the use of wildcards in the set_property constraints.  These wildcards [ together with step-5) ] allow the two set_property constraints to do everything we were trying to do with the two attribute lines in VHDL - and make it unnecessary to "Tcl-down (as you say)" to each separate instance of SYNC_2FF.

 

I will continue testing this method and let you know (via this post) if problems arise.

 

....many safe and happy journeys to you and your tardis

 

 

PS. thanks markcurry for your comments

Historian
Posts: 4,540
Registered: ‎01-23-2009

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

I looked at the AR. I think we need to make sure we are keeping this in context.

 

The AR says that the ASYNC_REG property doesn't work in this case - this is a specific case where the code is instantiating FDRE cells directly in a generate loop. Apparently (and I am not a VHDL expert) you cannot set a property on a primitive that is instantiated in a generate loop.

 

When using inference of registers, you use a VHDL signal as the signal that will become the register (the signal george when used in a proper clocked process will create the flip-flop george_reg). My understanding is that you can set the ASYNC_REG property on george, and that will propagate to the cell george_reg.

 

In the AR's case, they were setting the ASYNC_REG attribute on the signals that will become the nets connecting these instantiated primitive cells together, which doesn't do anything since the attribute needs to be applied to cells. The attribute was not being applied to the instantiated cells themselves (which can't be done in a generate loop). It is clearly also not being applied to a signal that infers the flip-flops, since they aren't inferring flip-flops, they are directly instantiating the FDRE).

 

So, the AR is saying that for this particular coding style, the only option is to do it in Tcl.

 

But if you are inferring flip-flops (which is probably the more common case), this AR doesn't apply.

 

Now, there may be additional problems associated with the ASYNC_REG property in certain versions of the tool (I haven't personally seen any), but we need to be careful not to extrapolate the case shown in this AR to the statement that "ASYNC_REG cannot be applied in the RTL code".

 

Avrum

Advisor
Posts: 566
Registered: ‎01-22-2015

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

avrumw:

 

Thanks for clarifying the AR.  After rereading it, I see that it is for a rather special case of VHDL coding.

 

I believe that the major complaint in this post is that for the common case of "inference of registers", the VHDL method (an attribute statement) for setting the ASYNC_REG property is not working reliably.  Specifically, I have observed it fail many times in Vivado v2014.2.  drjohnsmith says it works unreliably up thru Vivado v2015.4.

 

For these older versions of Vivado, the consensus of this post seems to be that XDC(Tcl) constraints are a reliable method of setting the ASYNC_REG property.   Do you see anything wrong with the XDC(Tcl) constraints described in my last post for setting the ASYNC_REG property?

Historian
Posts: 4,540
Registered: ‎01-23-2009

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

[ Edited ]

Do you see anything wrong with the XDC(Tcl) constraints described in my last post for setting the ASYNC_REG property?

 

With all the restrictions you mentioned, it should be OK, but I am generally uncomfortable with that "open" a wildcard. So here is an alternative (which should be pretty foolproof).

 

# Get all the instances of the entity "SYNC_2FF" wherever they are in the hierarchy

 

set sync_inst [get_cells -hier -filter {(ORIG_REF_NAME == SYNC_2FF) || (REF_NAME == SYNC_2FF)}]

 

# Set the ASYNC_REG property on all the cells named "sig_meta_reg" and "sigb_reg" in the instances identified above

set_property ASYNC_REG TRUE [get_cells [join $sync_inst "/sig_meta_reg "]]

set_property ASYNC_REG TRUE [get_cells [join $sync_inst "/sigb_reg "]]

 

# Note: the spaces after sig_meta and sigb inside the quotes are important...

 

[edited to add the slash in front of the flip-flop names and add the _reg]

Avrum

Scholar
Posts: 2,690
Registered: ‎07-09-2009

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

Just catching up.

  yes the ar is a special case, but it came about from the general problem thats still shown, 

      despite whats said, you can not use the async reg attribute n the vhdl code, you have to use the tcl approach.

 

the tcl is 'great' / 'powerful' tool 

 

BUT 

 

and its a big but, 

 

the general case is mentioned.

 

VHDL modules are meant to be re usable,

 

If I have a re usable module that needs re synchronisers in it, 

    

If I could use the VHDL approach, then the module is re usable.

   If I have to use the TCL approach, 

        I have to what, put documentation into prompt the user how to use the module and write the TCL code,

            and if there are more than one instance , do I have to put the path to each block into the tcl ?

                  and I have to also set the TCL such that the registers are not absorbed.

 

we just need the async_reg  attribute statement to work in vivado please 

 

I have not made it work so far, would love an example in vhdl that did work

 

Advisor
Posts: 566
Registered: ‎01-22-2015

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

Avrum:  Thanks for the “more focused” XDC(Tcl) constraints used to set the ASYNC_REG property.

 

For other readers of this post:   You can use commands similar to “join [get_cells -hier *sig_meta_reg] \n” in the Vivado Tcl Console to generate reports. These reports are a good check (I think) that the “set_property ASYNC_REG TRUE… ” constraints are catching all (and only) the instances of SYNC_2FF.

 

If the “VHDL attribute” method were working, I would prefer to use it instead of the XDC(Tcl) method for setting the ASYNC_REG property - for all the reasons giving by drjohnsmith.

 

For Vivado, does Xilinx have plans to test/fix the “VHDL attribute” method of setting the ASYNC_REG property?

Highlighted
Historian
Posts: 4,540
Registered: ‎01-23-2009

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

[ Edited ]

You can use commands similar to “join [get_cells -hier *sig_meta_reg] \n” in the Vivado Tcl Console to generate reports.

 

(slightly off the main topic, but useful none-the-less)

 

Agreed.

 

However, if you are in the Tcl console in the Vivado GUI, I prefer

 

show_objects [get_cells -hier *signal_meta_reg]

 

(keeping with the same example)

 

This generates an interactive "Find Results" window which shows all the objects found by the command. Within this window, you can click on each object to select it - when an object is selected, you can see its properties in the property window.

 

You can also select objects in a similar fashion using the select_objects command. When selected, objects are highlighted in all the graphics views (the schematic viewer, the die viewer, the hierarchy viewer, etc...). So,

 

select_objects [get_cells -hier *signal_meta_reg]

 

would select all the cells that match the name.

 

Its inverse is "get_selected_objects", which returns the list of objects that are selected. This can be very useful if you want to execute the same command on different things in the schematic window. For example, I often use

 

get_clocks -of_objects [get_selected_objects]

 

You can then re-run this command after clicking on different clock nets or pins in your design schematic to easily find which clocks propagate to that net or pin (very useful for visualizing and debugging clock crossing circuits).

 

Another good use of these commands is

 

select_objects [get_nets -segments [get_selected_objects]]

 

When you click on a net in the schematic viewer, it only selects the net segment. If you want to see where the whole net goes (passing in and out of levels of hierarchy), then you can use the above command.

 

(These are a few of the commands in my list of favorite Tcl commands)

 

Avrum

Advisor
Posts: 566
Registered: ‎01-22-2015

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

Avrum:  Thanks for the list of cool Tcl commands.  -simple and very useful.  I think they go hand-in-hand with the XDC(Tcl) constraints we are talking about (giving us confidence that the constraints are doing what we want).

 

-back the "VHDL attribute" method of setting ASYNC_REG.   I see VHDL attribute statements all the time in the instantiation templates for Xilinx/Vivado IP HDL code.  Hence, the use of VHDL attribute statements is not specific to setting the ASYNC_REG property. 

 

Is there anything further I can do to encourage Xilinx to look into this apparent problem of using VHDL attribute statements to set the ASYNC_REG property?

Advisor
Posts: 566
Registered: ‎01-22-2015

Re: Setting ASYNC_REG in VHDL for Two-Flop Synchronizer

I have migrated my project from Vivado v2014.2 to Vivado v2016.1.  

 

In each of several implemention runs, I find that the VHDL attribute statments are now setting the ASYNC_REG property correctly (ie. keeping registers of the 2FF synchronizer together in the same slice).  

 

If future problems occur then I will update this post.