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Participant
Participant
305 Views
Registered: ‎06-04-2020

Setup Violation

I have a slack of 

Inter clock setup violation as follows:

WNS: -0.448

the clock paths which are failing are the  outputs of MMCM so I cant group them into False path or async path.

How do I resolve this clock path

failing path.PNG
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4 Replies
Scholar
Scholar
290 Views
Registered: ‎08-07-2014

@Harish_Algat ,

one minute...............why are you feeding the data input (D) of the SRL with a clock signal(clkout2 from MMCM) ?

SRL16 - https://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

 

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Participant
Participant
282 Views
Registered: ‎06-04-2020

this is not my design So I have No idea
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Scholar
Scholar
272 Views
Registered: ‎08-07-2014

this is not my design So I have No idea

Same here, is it not? Then shouldn't you ask the person who has the idea ?

I have just pointed out a likely anomaly.

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Participant
Participant
215 Views
Registered: ‎06-04-2020

the violatons are because of Latch clock gating which is leading high clock skew
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