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Visitor randre
Visitor
1,870 Views
Registered: ‎07-12-2017

Slack saturation

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I synthesized some code with Vivado 2016.4. I constrained the only one clock i have, obtaining a negative slack.

 

(create_clock -period 8.000 -name clk -waveform {0.000 4.000} [get_ports clk])

 

FOTO 1.png

 

Then i tried to lower the clock frequency to obtain a positive slack. I tried to calculate the maxinum clock frequency with fmax = 1 / (Tck – WNS ) but I still obtained a negative slack:

 

FOTO 2.png

 

So i tried to lower a lot the clock frequency but the slack remains fixed to a certain negative value, indipendently to the clock frequency:

 

FOTO 3.png

 

Paths with negative slack are all related to a block wich has the main clock as input. It returns a 60 seconds clock as output (used as input by a downstream counter):

 

FOTO 4.png

 

This is the code of that block:

 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity clk_60s is	 
	generic( f_ck_in  : positive := 125000000;  --input freq. in hertz
	         t_ck_out : positive := 60  --output clock period in seconds	
         	); 	
		   					    
	port(
	 clk125Mhz : in  std_logic;
	 clk60s    : out std_logic := '0'
	);
end clk_60s;

architecture arc of clk_60s is

signal count : integer := 0;	 --counter signal
signal out_state: std_logic := '0'; 

begin
	
	increase: process(clk125Mhz)	 begin
	if (clk125Mhz = '1') then cont <= count + 1;	
	   if (count = f_ck_in * t_ck_out/2) then out_state <= not out_state; clk60s <= out_state; end if; --i divide by 2 to have a  50% duty cycle
    end if;
	end process increase;

end arc;

 

What do you think I have to check to solve this issue? Thank you.

 

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1 Solution

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Explorer
Explorer
3,201 Views
Registered: ‎07-14-2014

Re: Slack saturation

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I think what you have there would not synthesis into synchronous logic and would therefore give you timing problems,

 

I think you might have more luck with the the following;

increase: process(clk125Mhz)
begin
  if rising_edge(clk125Mhz) then
    cont <= count + 1;	
    if (count = f_ck_in * t_ck_out/2) then
      out_state <= not out_state;
      clk60s <= out_state;
    end if; --i divide by 2 to have a  50% duty cycle
  end if;
end process increase;

The key part is the rising_edge(clk125Mhz). This should then synthesis synchronous logic and hopefully meet timing

 

Regards

 

Simon

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3 Replies
Highlighted
Explorer
Explorer
3,202 Views
Registered: ‎07-14-2014

Re: Slack saturation

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I think what you have there would not synthesis into synchronous logic and would therefore give you timing problems,

 

I think you might have more luck with the the following;

increase: process(clk125Mhz)
begin
  if rising_edge(clk125Mhz) then
    cont <= count + 1;	
    if (count = f_ck_in * t_ck_out/2) then
      out_state <= not out_state;
      clk60s <= out_state;
    end if; --i divide by 2 to have a  50% duty cycle
  end if;
end process increase;

The key part is the rising_edge(clk125Mhz). This should then synthesis synchronous logic and hopefully meet timing

 

Regards

 

Simon

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Visitor randre
Visitor
1,812 Views
Registered: ‎07-12-2017

Re: Slack saturation

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Hi Simon. Thanks for your answer.

 

Your suggestions solved my problem. 

 

What do you mean when you say " what you have there would not synthesis into synchronous logic and would therefore give you timing problems"?

Has this kind of problem a name so i can search it in literature? 

 

I really thank you for your time.

 

Regards,

 

Andrea.

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Explorer
Explorer
1,804 Views
Registered: ‎07-14-2014

Re: Slack saturation

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As I understand it the synthesis engine looks at the way code is written and infers the required hardware from that.

 

If you synthesise both processes and then look at the schematic that is created (elaborated design schematic may give you more of a clue as to what is going on at the gate level) then you will get some idea of what the tool was trying to do with your code.

 

In general (for VHDL at least) you need a if rising_edge(clk) type statement to infer a flip flop (synchronous design). The code you posted will generate an asynchronous sea of gates that attempts to count as fast as possible when clk125MHz was high.

 

Check out Chapter 4 (HDL Coding Techniques (at least it's chapter 4 in the document version I'm looking at anyway) in UG901 Synthesis User Guide for more detailed information

 

Regards

 

Simon

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