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Adventurer
Adventurer
3,914 Views
Registered: ‎12-22-2008

Some questions about the timing analysis of the ddr sdram controller which generated by MIG

I am doing a project about using Virtex2Pro to control the ddr sdram and I use the MIG to generate the controller. Let me introduce the controller first. The controller use one DCM to create two clock, i.e.,clk0 and clk90 and afterwards use two inverter to create clk180 and clk270 respectively. And xilinx also give a macro(in the form of edn) to connect between DCM output and BUFG to achieve high-speed DDR timing budgets. But I have some question about the timing analysis as follow:

 

1 Only one timing constraint about the period has been found in the UCF:
//the start of the relevant content in the UCF
NET "mem_interface_top0/sys_clk_ibuf" TNM_NET = FFS (*) "SYS_CLK";
TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 8.00000 ns HIGH 50 %;
//the end of the relevant content in the UCF

 

However, in the timing analysis file(twr file), I find the following content:

 

//the start of the relevant content in the TWR file
================================================================================
Timing constraint: TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm =
PERIOD TIMEGRP        
"mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm" TS_SYS_CLK        
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk90dcm
= PERIOD TIMEGRP        
"mem_interface_top0_infrastructure_top0_clk_dcm0_clk90dcm" TS_SYS_CLK        
PHASE 2 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_0
= PERIOD TIMEGRP        
"mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_0" TS_SYS_CLK        
HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint:
TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk90dcm_0 = PERIOD TIMEGRP 
       "mem_interface_top0_infrastructure_top0_clk_dcm0_clk90dcm_0"        
TS_SYS_CLK PHASE 2 ns HIGH 50%;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_1
= PERIOD TIMEGRP        
"mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_1" TS_SYS_CLK        
HIGH 50%;

 3097 paths analyzed, 580 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   7.594ns.
...
...
//the end of the relevant content in the TWR file

 

So, my first question is how those constraints have been created automatically especially considering that for the first four constraint, no paths have been analyzed.

 

2 My second question is the minimum period based on one constraint is 7.594 and I don't know how this period can be calculated. Generally, if you have only one clock in the domain, the calculation of this period is very simple: minimum period=data path - clock path skew + uncertainty. But in this case which has several clock domain, I cannot calculate out 7.594 based on the paths listed below. The following is the detailed report about this constraint.

 

//the start of the twr file
================================================================================
Timing constraint: TS_mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_1
= PERIOD TIMEGRP        
"mem_interface_top0_infrastructure_top0_clk_dcm0_clk0dcm_1" TS_SYS_CLK        
HIGH 50%;

 3097 paths analyzed, 580 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   7.594ns. (I don't know how this period can be calculated based on the following information)
--------------------------------------------------------------------------------
Slack:                  0.145ns (requirement - (data path - clock path skew + uncertainty))
  Source:               mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_5 (FF)
  Destination:          ddr_controller_fsm0/read_dat_o_5 (FF)
  Requirement:          2.000ns
  Data Path Delay:      1.837ns (Levels of Logic = 0)
  Clock Path Skew:      -0.018ns (3.267 - 3.285)
  Source Clock:         clk90_int rising at 2.000ns
  Destination Clock:    clk_int falling at 4.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_5 to ddr_controller_fsm0/read_dat_o_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y51.XQ       Tcko                        0.374   u_data_o<5>
                                                                                        mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_5
    SLICE_X3Y62.BY       net (fanout=1)        1.261   u_data_o<5>
    SLICE_X3Y62.CLK      Tdick                       0.202   read_dat_o_5_OBUF
                                                                                       ddr_controller_fsm0/read_dat_o_5
    -------------------------------------------------  ---------------------------
    Total                                                               1.837ns (0.576ns logic, 1.261ns route)
                                                                                        (31.4% logic, 68.6% route)

--------------------------------------------------------------------------------
Slack:                  0.203ns (requirement - (data path - clock path skew + uncertainty))
  Source:               mem_interface_top0/ddr1_top0/controller0/auto_ref_wait (FF)
  Destination:          ddr_controller_fsm0/u_addr_22 (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.797ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_int falling at 4.000ns
  Destination Clock:    clk_int rising at 8.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: mem_interface_top0/ddr1_top0/controller0/auto_ref_wait to ddr_controller_fsm0/u_addr_22
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y69.XQ       Tcko                       0.374   auto_ref_req
                                                                                      mem_interface_top0/ddr1_top0/controller0/auto_ref_wait
    SLICE_X1Y70.F4       net (fanout=8)        0.643   auto_ref_req
    SLICE_X1Y70.X        Tilo                          0.288   u_cmd<1>
                                                                                      ddr_controller_fsm0/CS_FSM_Out1111
    SLICE_X1Y70.G2       net (fanout=3)        0.159   ddr_controller_fsm0/N5
    SLICE_X1Y70.Y        Tilo                            0.313   u_cmd<1>
                                                                                     ddr_controller_fsm0/u_addr_mux0000<0>21
    SLICE_X10Y79.G4      net (fanout=25)       1.707   ddr_controller_fsm0/N3
    SLICE_X10Y79.Y       Tilo                             0.313   u_addr<22>
                                                                                          ddr_controller_fsm0/u_addr_mux0000<22>1
    SLICE_X10Y79.DY      net (fanout=1)        0.000   ddr_controller_fsm0/u_addr_mux0000<22>
    SLICE_X10Y79.CLK     Tdyck                      0.000   u_addr<22>
                                                                                         ddr_controller_fsm0/u_addr_22
    -------------------------------------------------  ---------------------------
    Total                                                                 3.797ns (1.288ns logic, 2.509ns route)
                                                                                          (33.9% logic, 66.1% route)

--------------------------------------------------------------------------------
Slack:                  0.266ns (requirement - (data path - clock path skew + uncertainty))
  Source:               mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_12 (FF)
  Destination:          ddr_controller_fsm0/read_dat_o_12 (FF)
  Requirement:          2.000ns
  Data Path Delay:      1.720ns (Levels of Logic = 0)
  Clock Path Skew:      -0.014ns (3.267 - 3.281)
  Source Clock:         clk90_int rising at 2.000ns
  Destination Clock:    clk_int falling at 4.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_12 to ddr_controller_fsm0/read_dat_o_12
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y52.YQ       Tcko                         0.374   u_data_o<13>
                                                                                mem_interface_top0/ddr1_top0/data_path0/data_read0/first_sdr_data_12
    SLICE_X3Y63.BY       net (fanout=1)        1.144   u_data_o<12>
    SLICE_X3Y63.CLK      Tdick                     0.202   read_dat_o_12_OBUF
                                                                                    ddr_controller_fsm0/read_dat_o_12
    -------------------------------------------------  ---------------------------
    Total                                                               1.720ns (0.576ns logic, 1.144ns route)
                                                                                         (33.5% logic, 66.5% route)

--------------------------------------------------------------------------------

 

 

Those problems have confused me for some time. I really appreciate if someone can give me some advice.

 

Message Edited by zhj1985 on 04-04-2009 05:01 AM
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