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Adventurer
Adventurer
4,687 Views
Registered: ‎06-30-2013

Source Synchronous Input - OFFSET IN Hold Time violations

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Background:

 

I have implemented a multi-channel source synchronous DDR interface between ADC channels and FPGA fabric.  My implementation, as constrained, is failing several paths for each OFFSET IN constraint.

 

The project is implemented in ISE 14.6 using a Zynq XC7Z020, -1 speed grade.  This is ARTIX fabric.

This is a legacy project and I realize that Vivavdo is the better tool but cannot afford to migrate and must fix it in ISE.

 

General Data and Clock implementation:

 

I have implemented the following structures.  For the DDR data paths,  the chain is

IBUFDS -->  IDELAYE[fixed delay= 14, pattern=DATA] --> IDDR.D[SAME EDGE, PIPELINED]

For the clock path:

IBUFGDS -->  IDELAYE[fixed delay= 0, pattern=CLOCK] --> BUFIO   --> IDDR.CLK
               --> BUFR  --> to other logic connected to IDDR.Q data outputs
              
As an interesting note, I used the Select IO Wizard to help me build the above interfaces but found that it instantiated
a BUFIO and BUFR driven by the zero delay IDELAYE element for the clock but used the BUFR and not the BUFIO to drive to the IDDR clock. 
I modified the VHD file to use BUFIO clock output to drive the IDDR clock as described below because I believe my timing required a BUFIO

 

Details:

 

The ADCs operate at a 150MHz sampling rate and this is the frequency of the source synchronous clock.  The data sheet gives the minimum setup time as 1.15ns and the minimum hold time as 1.1ns.  This gives a minimum data window of 2.25ns.

 

In the data sheet for the ARTIX fabric, I found the Tpscs/Tphcs spec (page 47) for the Data Input Setup and Hold Times
Relative to a Forwarded lock Input Pin using a BUFIO to -0.38/1.76ns for the -1 speed grade at 1.0V.  This is the reason I chose to modify the Select IO wizard to drive the IDDR elements form the BUFIO clock.  WAS THIS OK OR DID I MAKE AN ERROR?

 

From the above ARTIX spec my understanding is that the data can actually be setup after the
clock edge by 0.38ns so the total window for valid data capture is 1.76-0.38= 1.38ns.  This 1.38ns data capture window is smaller
than the 2.25ns ADC window which should be a good thing. 

 

But I need to shift the data to center the windows.  The center of the capture window is 0.38ns + 1.38ns/2 = 1.07ns but the ceneter of the ADC data valid window is -1.1ns + (2.25ns)/2 = 0.025ns.  So I need to shift the data using the IDELAYE element by 1.07ns-0.025ns= 1.045ns.  Below are example constraints for one channel:

 

 

NET "CLK_AB_P" TNM_NET= "CLK_FMC_AB" ;
TIMESPEC "TS_CLK_FMC_AB" = PERIOD "CLK_FMC_AB" 6.666 ns HIGH 50% INPUT_JITTER 30 ps;

 

NET "system_i/zed_panther_0/zed_panther_0/zed_top_0/CHA_N[*]" TNM = "adc_data_a";
NET "system_i/zed_panther_0/zed_panther_0/zed_top_0/CHA_P[*]" TNM = "adc_data_a";

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE CLK_AB_P RISING ;
TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE CLK_AB_P FALLING ;

 

 

I feed each IDELAYE element with a 200MHZ reference clock so the tap delay is 78+/- 5ps.  I chose to set the IDELAYE fixed delay to 14 taps because 1.045ns/78ps = 13.4 and I rounded up.  IS MY DESIGN APPROACH SO FAR SOUND?  IF NOT, WHY?

 

Timing Results:

 

Unfortunately, when I looked at the timing results for the implemented design, I see that every path for the positive and negative data pins is failing to meet the HOLD time specified.  This is true for both the RISING and FALLING clock edges.  The slack times for the HOLD paths are around -0.7ns and I give the details for one failing path for the RISING edge of CLK_AB_P below.

When I look at the implemented design, I see that the location of the IO pin, its IBUFDS, the IDELAYE and IDDR elements
 are about as close as possible.  It appears to me that the clock path has too much delay????  HOW DO I FIX THIS PROBLEM????  Am I missing something fundamental.  I experimented by driving the IDDR's clock input with the BUFR output instead of the BUFIO output.  This is the way the Wizard originally configured the elements.  In this case the timing violations improve significantly and there are fewer hold violations and the failures are less than 0.32ns  Does this mean that I should be using the BUFR and not the BUFIO???
 
One other timing analyzer tool related question I have is does the timing analyzer take into account the actual specified delay for each IDELAYE element based upon the fixed delay  set during implementation?  In other words,  the 14 tap delay I specify equates to 14 * 78ps = 1.092ns and is that factored into the analysis.  This is the instantiation of the data path IDELAYE elements from the generate loop.

 

 

idelaye2_bus : IDELAYE2
       generic map (
         CINVCTRL_SEL           => "FALSE",                        -- TRUE, FALSE
         DELAY_SRC              => "IDATAIN",                        -- IDATAIN, DATAIN
         HIGH_PERFORMANCE_MODE  => "FALSE",         -- TRUE, FALSE
         IDELAY_TYPE            => "VAR_LOAD",                   -- FIXED, VARIABLE, or VAR_LOADABLE
         IDELAY_VALUE           => 14,                                   -- 0 to 31 --CMJ
         REFCLK_FREQUENCY       => 200.0,
         PIPE_SEL               => "FALSE",
         SIGNAL_PATTERN         => "DATA"                         -- CLOCK, DATA
         )
         port map (
         DATAOUT                => data_in_from_pins_delay(pin_count),
         DATAIN                 => '0',                                                       -- Data from FPGA logic
         C                      => DELAY_CLK,
         CE                     => in_delay_ce(pin_count),                          --IN_DELAY_DATA_CE,
         INC                    => in_delay_inc_dec(pin_count),                 --IN_DELAY_DATA_INC,
         IDATAIN                => data_in_from_pins_int  (pin_count),    -- Driven by IOB
         LD                     => IN_DELAY_RESET,
         REGRST                 => IO_RESET,
         LDPIPEEN               => '0',
         CNTVALUEIN             => in_delay_tap_in_int(pin_count),       --IN_DELAY_TAP_IN,
         CNTVALUEOUT            => in_delay_tap_out_int(pin_count),   --IN_DELAY_TAP_OUT,
         CINVCTRL               => '0'
         );
 
 Thanks  in advance for any help!

 

Craig

 

 

 

############################################################################################

Example failing Hold Constraint

############################################################################################

Hold Paths: TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"
        "RISING";
--------------------------------------------------------------------------------
Slack (hold path):      -0.691ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               CHA_P[3] (PAD)
  Destination:          system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].iddr_inst (FF)
  Destination Clock:    system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/clk_in_int_buf rising at 0.000ns
  Requirement:          1.100ns
  Data Path Delay:      2.312ns (Levels of Logic = 2)(Component delays alone exceeds constraint)
  Clock Path Delay:     4.074ns (Levels of Logic = 3)
  Clock Uncertainty:    0.029ns

  Clock Uncertainty:          0.029ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.030ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: CHA_P[3] to system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].iddr_inst
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    L21.I                Tiopi                 0.867   CHA_P[3]
                                                       CHA_P[3]
                                                       system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].ibufds_inst/IBUFDS
    IDELAY_X1Y80.IDATAIN net (fanout=1)        0.000   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/data_in_from_pins_int[3]
    IDELAY_X1Y80.DATAOUT Tiddo_IDATAIN         1.636   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].idelaye2_bus
                                                       system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].idelaye2_bus
    ILOGIC_X1Y80.DDLY    net (fanout=1)        0.000   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/data_in_from_pins_delay[3]
    ILOGIC_X1Y80.CLK     Tiockdd     (-Th)     0.191   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/ch_a_adc_sdr_offset[3]
                                                       system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].iddr_inst
    -------------------------------------------------  ---------------------------
    Total                                      2.312ns (2.312ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path at Slow Process Corner: CLK_AB_P to system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/pins[3].iddr_inst
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M19.I                Tiopi                 0.905   CLK_AB_P
                                                       CLK_AB_P
                                                       system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/ibufds_clk_inst/IBUFDS
    IDELAY_X1Y74.IDATAIN net (fanout=1)        0.000   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/clk_in_int
    IDELAY_X1Y74.DATAOUT Tiddo_IDATAIN         0.815   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/idelaye2_clk
                                                       system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/idelaye2_clk
    BUFIO_X1Y5.I         net (fanout=2)        0.417   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/clk_in_int_delay
    BUFIO_X1Y5.O         Tbiocko_O             1.609   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/bufio_inst
                                                       system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/bufio_inst
    ILOGIC_X1Y80.CLK     net (fanout=14)       0.328   system_i/zed_panther_0/zed_panther_0/zed_top_0/sig_proc_top_0/chA_ddr/clk_in_int_buf
    -------------------------------------------------  ---------------------------
    Total                                      4.074ns (3.329ns logic, 0.745ns route)
                                                       (81.7% logic, 18.3% route)

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Adventurer
Adventurer
7,909 Views
Registered: ‎06-30-2013

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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Hi Avrum:

 

After performing the experimentation you suggested and tightening my constraints to account for the 52$ clock duty cycle and reducing my valid window time and OFFSET IN time to account for 50ps of routing skew, I was able to achieve almost 400 ps of positive slack on both set-up and hold times for all paths.  This was done with no clock IDELAYE, a BUFR on the clock path to the IDDR clock input and a reduction in the data path IDELAYE to 10 taps.

 

With your guidance my understanding of the fabric and the methodology to achieve timing closure is much improved.

 

I now believe my design is robust enough to handle device PVT and supply variations and will begin testing in the lab

 

Thank you for your support!

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Historian
Historian
4,679 Views
Registered: ‎01-23-2009

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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@cjavid,

 

It looks like you are in pretty good shape structurally.

 

Your observation that the BUFR timing is better than the BUFIO timing is consistent with what I have seen - with an IDDR you can definitely use the BUFR alone (and not use the BUFIO at all).

 

It is important to note two things about Tpscs/Tphcs:

  - it is not actually "guranteed". The final timing is determined by the results of static timing analysis (in this case trce). My experience is that the device doesn't actually conform to its own specifications (I have complained, but no one seems to want to address it). So the window required is actually slightly wider than the 1.38ns specified. In a Kintex device I have seen it be about 200ps larger and not in the "right" place (and again, better with the BUFR than with the BUFIO)

  - it assumes you don't need to use the IDELAY. Adding the IDELAY unfortunately adds a certain amount of uncompensated PVT delay, which increases the width of the required window further.

 

For the timing analysis, you don't tell us if you have margin on your setup checks or not - that is the big question. If the sum of your setup margin plus your hold margin is positive, then it is simply a matter of adjusting the IDELAY tap values to make this work.

 

If the sum is negative, you aren't necessarily toast (yet). Delaying the data is more costly (in terms of timing) than delaying the clock. In fact, in this case (in fact in most cases) I would be inclined to delay the clock not the data. Yes, your timing looks right (coming up with the 14 tap delay), but this adds TIDELAYPAT_JIT per tap to the delay. First make sure your IDELAY is in HIGH_PERFORMANCE mode. In this case, the jitter would be +/-70ps, which will cost you 140ps of margin on the interface.  So, if, your difference is less than 140ps, then you can get this to work (you will have to change your constraints, though, to make this happen).

 

Finally, while it makes logical sense to have an IDELAY on both clock and data (to have them cancel), according to the tools, this can make things worse. Forget about getting the "right" delay, and try to determine the viability of your interface first. Set all IDELAYs to 0, and try your interface with IDELAYs on the clock only, on the data only, and on both (you can even try neither, just in case you are lucky). If any of these solutions yields a positive sum on the setup and hold slack (other than the "no IDELAY" attempt, which would actually have to pass), then you have a chance.

 

Lets see where we get with this, and depending on the results, we can work on modifying the capture edge and constraints accordingly.

 

If none of these solutions yield positive slack, then you have a problem... There are solutions, but they get messy.

 

Avrum

Historian
Historian
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Registered: ‎01-23-2009

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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In other words,  the 14 tap delay I specify equates to 14 * 78ps = 1.092ns and is that factored into the analysis

 

So the answer is yes, but not exactly. The 78ps per tap is actually not accurate - that is the average. The first tap is actually quite a bit bigger, and the remaining taps are smaller. But the tool understands all of this and will add the appropriate propagation delay for the IDELAY based on the tap setting - it just may not be exactly 14*78 (although for larger taps values it tends to be pretty close),

 

Avrum

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Adventurer
Adventurer
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Registered: ‎06-30-2013

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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Hi Avrum:

 

As usual, your knowledge and clarity of response is unparalleled! 

 

OK, even with the BUFR driven clock to the IDDR, the sum of the negative hold slack and the positive setup slack is still negative in most cases.  So I guess adjusting the data path  IDELAY value is not going to work as you say.

 

I will experiment as you suggest and see what the STA says.  I am sure I will be back asking for additional help??

 

Thanks again,

 

Craig

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Adventurer
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Registered: ‎06-30-2013

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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Hi Avrum:

 

 

I changed the data delay from 14 to 18 taps and I now fail in setup and hold by a small amount - most failing by less than 100ps.  Some paths are now ok but not by much.  Below is the summary from TRCE.  Also, I just realized that I DID NOT have the IDELAYE set to high performance so I will change and re-analyze.

 

Any other suggestions or feedback welcome.

 

Craig

 

 

 

 

 

TIMEGRP "adc_data_c" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_CD_P"         "RISING";
Worst Case Data Window 2.449; Ideal Clock Offset To Actual Clock 0.046;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHC_N[0]          |    1.295(R)|      FAST  |    1.076(R)|      SLOW  |   -0.145|    0.024|       -0.084|
CHC_N[1]          |    1.237(R)|      FAST  |    1.131(R)|      SLOW  |   -0.087|   -0.031|       -0.028|
CHC_N[2]          |    1.222(R)|      FAST  |    1.151(R)|      SLOW  |   -0.072|   -0.051|       -0.010|
CHC_N[3]          |    1.256(R)|      FAST  |    1.112(R)|      SLOW  |   -0.106|   -0.012|       -0.047|
CHC_N[4]          |    1.266(R)|      FAST  |    1.106(R)|      SLOW  |   -0.116|   -0.006|       -0.055|
CHC_N[5]          |    1.249(R)|      FAST  |    1.124(R)|      SLOW  |   -0.099|   -0.024|       -0.038|
CHC_N[6]          |    1.215(R)|      FAST  |    1.149(R)|      SLOW  |   -0.065|   -0.049|       -0.008|
CHC_P[0]          |    1.292(R)|      FAST  |    1.079(R)|      SLOW  |   -0.142|    0.021|       -0.081|
CHC_P[1]          |    1.234(R)|      FAST  |    1.134(R)|      SLOW  |   -0.084|   -0.034|       -0.025|
CHC_P[2]          |    1.219(R)|      FAST  |    1.154(R)|      SLOW  |   -0.069|   -0.054|       -0.008|
CHC_P[3]          |    1.253(R)|      FAST  |    1.115(R)|      SLOW  |   -0.103|   -0.015|       -0.044|
CHC_P[4]          |    1.263(R)|      FAST  |    1.109(R)|      SLOW  |   -0.113|   -0.009|       -0.052|
CHC_P[5]          |    1.246(R)|      FAST  |    1.127(R)|      SLOW  |   -0.096|   -0.027|       -0.035|
CHC_P[6]          |    1.212(R)|      FAST  |    1.152(R)|      SLOW  |   -0.062|   -0.052|       -0.005|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.295|         -  |       1.154|         -  |   -0.145|   -0.054|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_c" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_CD_P"         "FALLING";
Worst Case Data Window 2.449; Ideal Clock Offset To Actual Clock 0.046;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHC_N[0]          |   -2.038(F)|      FAST  |    4.409(F)|      SLOW  |   -0.145|    0.024|       -0.084|
CHC_N[1]          |   -2.096(F)|      FAST  |    4.464(F)|      SLOW  |   -0.087|   -0.031|       -0.028|
CHC_N[2]          |   -2.111(F)|      FAST  |    4.484(F)|      SLOW  |   -0.072|   -0.051|       -0.010|
CHC_N[3]          |   -2.077(F)|      FAST  |    4.445(F)|      SLOW  |   -0.106|   -0.012|       -0.047|
CHC_N[4]          |   -2.067(F)|      FAST  |    4.439(F)|      SLOW  |   -0.116|   -0.006|       -0.055|
CHC_N[5]          |   -2.084(F)|      FAST  |    4.457(F)|      SLOW  |   -0.099|   -0.024|       -0.038|
CHC_N[6]          |   -2.118(F)|      FAST  |    4.482(F)|      SLOW  |   -0.065|   -0.049|       -0.008|
CHC_P[0]          |   -2.041(F)|      FAST  |    4.412(F)|      SLOW  |   -0.142|    0.021|       -0.081|
CHC_P[1]          |   -2.099(F)|      FAST  |    4.467(F)|      SLOW  |   -0.084|   -0.034|       -0.025|
CHC_P[2]          |   -2.114(F)|      FAST  |    4.487(F)|      SLOW  |   -0.069|   -0.054|       -0.008|
CHC_P[3]          |   -2.080(F)|      FAST  |    4.448(F)|      SLOW  |   -0.103|   -0.015|       -0.044|
CHC_P[4]          |   -2.070(F)|      FAST  |    4.442(F)|      SLOW  |   -0.113|   -0.009|       -0.052|
CHC_P[5]          |   -2.087(F)|      FAST  |    4.460(F)|      SLOW  |   -0.096|   -0.027|       -0.035|
CHC_P[6]          |   -2.121(F)|      FAST  |    4.485(F)|      SLOW  |   -0.062|   -0.052|       -0.005|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.038|         -  |       4.487|         -  |   -0.145|   -0.054|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_g" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_GH_P"         "RISING";
Worst Case Data Window 2.387; Ideal Clock Offset To Actual Clock 0.019;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHG_N[0]          |    1.232(R)|      FAST  |    1.133(R)|      SLOW  |   -0.082|   -0.033|       -0.025|
CHG_N[1]          |    1.224(R)|      FAST  |    1.144(R)|      SLOW  |   -0.074|   -0.044|       -0.015|
CHG_N[2]          |    1.227(R)|      FAST  |    1.138(R)|      SLOW  |   -0.077|   -0.038|       -0.020|
CHG_N[3]          |    1.232(R)|      FAST  |    1.133(R)|      SLOW  |   -0.082|   -0.033|       -0.025|
CHG_N[4]          |    1.238(R)|      FAST  |    1.127(R)|      SLOW  |   -0.088|   -0.027|       -0.031|
CHG_N[5]          |    1.222(R)|      FAST  |    1.146(R)|      SLOW  |   -0.072|   -0.046|       -0.013|
CHG_N[6]          |    1.227(R)|      FAST  |    1.141(R)|      SLOW  |   -0.077|   -0.041|       -0.018|
CHG_P[0]          |    1.229(R)|      FAST  |    1.136(R)|      SLOW  |   -0.079|   -0.036|       -0.022|
CHG_P[1]          |    1.221(R)|      FAST  |    1.147(R)|      SLOW  |   -0.071|   -0.047|       -0.012|
CHG_P[2]          |    1.224(R)|      FAST  |    1.141(R)|      SLOW  |   -0.074|   -0.041|       -0.016|
CHG_P[3]          |    1.229(R)|      FAST  |    1.136(R)|      SLOW  |   -0.079|   -0.036|       -0.022|
CHG_P[4]          |    1.235(R)|      FAST  |    1.130(R)|      SLOW  |   -0.085|   -0.030|       -0.028|
CHG_P[5]          |    1.219(R)|      FAST  |    1.149(R)|      SLOW  |   -0.069|   -0.049|       -0.010|
CHG_P[6]          |    1.224(R)|      FAST  |    1.144(R)|      SLOW  |   -0.074|   -0.044|       -0.015|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.238|         -  |       1.149|         -  |   -0.088|   -0.049|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_g" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_GH_P"         "FALLING";
Worst Case Data Window 2.387; Ideal Clock Offset To Actual Clock 0.019;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHG_N[0]          |   -2.101(F)|      FAST  |    4.466(F)|      SLOW  |   -0.082|   -0.033|       -0.025|
CHG_N[1]          |   -2.109(F)|      FAST  |    4.477(F)|      SLOW  |   -0.074|   -0.044|       -0.015|
CHG_N[2]          |   -2.106(F)|      FAST  |    4.471(F)|      SLOW  |   -0.077|   -0.038|       -0.020|
CHG_N[3]          |   -2.101(F)|      FAST  |    4.466(F)|      SLOW  |   -0.082|   -0.033|       -0.025|
CHG_N[4]          |   -2.095(F)|      FAST  |    4.460(F)|      SLOW  |   -0.088|   -0.027|       -0.031|
CHG_N[5]          |   -2.111(F)|      FAST  |    4.479(F)|      SLOW  |   -0.072|   -0.046|       -0.013|
CHG_N[6]          |   -2.106(F)|      FAST  |    4.474(F)|      SLOW  |   -0.077|   -0.041|       -0.018|
CHG_P[0]          |   -2.104(F)|      FAST  |    4.469(F)|      SLOW  |   -0.079|   -0.036|       -0.022|
CHG_P[1]          |   -2.112(F)|      FAST  |    4.480(F)|      SLOW  |   -0.071|   -0.047|       -0.012|
CHG_P[2]          |   -2.109(F)|      FAST  |    4.474(F)|      SLOW  |   -0.074|   -0.041|       -0.016|
CHG_P[3]          |   -2.104(F)|      FAST  |    4.469(F)|      SLOW  |   -0.079|   -0.036|       -0.022|
CHG_P[4]          |   -2.098(F)|      FAST  |    4.463(F)|      SLOW  |   -0.085|   -0.030|       -0.028|
CHG_P[5]          |   -2.114(F)|      FAST  |    4.482(F)|      SLOW  |   -0.069|   -0.049|       -0.010|
CHG_P[6]          |   -2.109(F)|      FAST  |    4.477(F)|      SLOW  |   -0.074|   -0.044|       -0.015|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.095|         -  |       4.482|         -  |   -0.088|   -0.049|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"         "RISING";
Worst Case Data Window 2.453; Ideal Clock Offset To Actual Clock 0.067;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHA_N[0]          |    1.250(R)|      FAST  |    1.114(R)|      SLOW  |   -0.100|   -0.014|       -0.043|
CHA_N[1]          |    1.255(R)|      FAST  |    1.109(R)|      SLOW  |   -0.105|   -0.009|       -0.048|
CHA_N[2]          |    1.280(R)|      FAST  |    1.090(R)|      SLOW  |   -0.130|    0.010|       -0.070|
CHA_N[3]          |    1.232(R)|      FAST  |    1.132(R)|      SLOW  |   -0.082|   -0.032|       -0.025|
CHA_N[4]          |    1.249(R)|      FAST  |    1.118(R)|      SLOW  |   -0.099|   -0.018|       -0.041|
CHA_N[5]          |    1.318(R)|      FAST  |    1.053(R)|      SLOW  |   -0.168|    0.047|       -0.108|
CHA_N[6]          |    1.243(R)|      FAST  |    1.124(R)|      SLOW  |   -0.093|   -0.024|       -0.035|
CHA_P[0]          |    1.247(R)|      FAST  |    1.117(R)|      SLOW  |   -0.097|   -0.017|       -0.040|
CHA_P[1]          |    1.252(R)|      FAST  |    1.112(R)|      SLOW  |   -0.102|   -0.012|       -0.045|
CHA_P[2]          |    1.277(R)|      FAST  |    1.093(R)|      SLOW  |   -0.127|    0.007|       -0.067|
CHA_P[3]          |    1.229(R)|      FAST  |    1.135(R)|      SLOW  |   -0.079|   -0.035|       -0.022|
CHA_P[4]          |    1.246(R)|      FAST  |    1.121(R)|      SLOW  |   -0.096|   -0.021|       -0.038|
CHA_P[5]          |    1.315(R)|      FAST  |    1.056(R)|      SLOW  |   -0.165|    0.044|       -0.105|
CHA_P[6]          |    1.240(R)|      FAST  |    1.127(R)|      SLOW  |   -0.090|   -0.027|       -0.032|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.318|         -  |       1.135|         -  |   -0.168|   -0.035|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"         "FALLING";
Worst Case Data Window 2.453; Ideal Clock Offset To Actual Clock 0.067;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHA_N[0]          |   -2.083(F)|      FAST  |    4.447(F)|      SLOW  |   -0.100|   -0.014|       -0.043|
CHA_N[1]          |   -2.078(F)|      FAST  |    4.442(F)|      SLOW  |   -0.105|   -0.009|       -0.048|
CHA_N[2]          |   -2.053(F)|      FAST  |    4.423(F)|      SLOW  |   -0.130|    0.010|       -0.070|
CHA_N[3]          |   -2.101(F)|      FAST  |    4.465(F)|      SLOW  |   -0.082|   -0.032|       -0.025|
CHA_N[4]          |   -2.084(F)|      FAST  |    4.451(F)|      SLOW  |   -0.099|   -0.018|       -0.041|
CHA_N[5]          |   -2.015(F)|      FAST  |    4.386(F)|      SLOW  |   -0.168|    0.047|       -0.108|
CHA_N[6]          |   -2.090(F)|      FAST  |    4.457(F)|      SLOW  |   -0.093|   -0.024|       -0.035|
CHA_P[0]          |   -2.086(F)|      FAST  |    4.450(F)|      SLOW  |   -0.097|   -0.017|       -0.040|
CHA_P[1]          |   -2.081(F)|      FAST  |    4.445(F)|      SLOW  |   -0.102|   -0.012|       -0.045|
CHA_P[2]          |   -2.056(F)|      FAST  |    4.426(F)|      SLOW  |   -0.127|    0.007|       -0.067|
CHA_P[3]          |   -2.104(F)|      FAST  |    4.468(F)|      SLOW  |   -0.079|   -0.035|       -0.022|
CHA_P[4]          |   -2.087(F)|      FAST  |    4.454(F)|      SLOW  |   -0.096|   -0.021|       -0.038|
CHA_P[5]          |   -2.018(F)|      FAST  |    4.389(F)|      SLOW  |   -0.165|    0.044|       -0.105|
CHA_P[6]          |   -2.093(F)|      FAST  |    4.460(F)|      SLOW  |   -0.090|   -0.027|       -0.032|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.015|         -  |       4.468|         -  |   -0.168|   -0.035|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

 

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Registered: ‎06-30-2013

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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Hi Avrum:

 

I re-implemented the project wit the following and included the timing summary for the DDR paths at the end.

 

The timing was generated with the following:

 

Set the IDELAYE elements for the clock and data to High Performance Mode

Set the data delay to 18 taps (same as previous run)

Used BUFR to feed IDDR clock (same as previous run)

 

Note that for all three ADC data channels ALL paths have positive HOLD slack and only some paths have negative SETUP slack. 

The timing getting pretty close but what options do I have to improve?  Ii appears from the timing summary below that I have more positive HOLD slack that negative setup slack for the failing cases.  Should I consider individual settings each data bit IDELAYE element.  That seems messy. 

 

Of course, if I change my OFFSET IN constraints from 1.15ns/2.25ns to 1.25ns/2.35ns I get zero timing errors in all the paths. 

 

I have run two pieces of hardware using the timing shown below and have not seen any data errors over about 24 hours.  Still, I am nervous that I do not yet have a robust design.  I believe I should meet timing with the worst case timing specified by the ADC manufacturer even though I can meet timing is very close to the worst case.

 

Thank you again for your help,

 

Craig

 

 

 

 

TIMEGRP "adc_data_c" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_CD_P"         "RISING";
Worst Case Data Window 2.269; Ideal Clock Offset To Actual Clock 0.055;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process                       |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner            |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHC_N[0]          |    1.214(R)|      FAST  |    0.977(R)|      SLOW  |   -0.064|    0.123|       -0.094|
CHC_N[1]          |    1.156(R)|      FAST  |    1.032(R)|      SLOW  |   -0.006|    0.068|       -0.037|
CHC_N[2]          |    1.141(R)|      FAST  |    1.052(R)|      SLOW  |    0.009|    0.048|       -0.020|
CHC_N[3]          |    1.175(R)|      FAST  |    1.013(R)|      SLOW  |   -0.025|    0.087|       -0.056|
CHC_N[4]          |    1.185(R)|      FAST  |    1.007(R)|      SLOW  |   -0.035|    0.093|       -0.064|
CHC_N[5]          |    1.168(R)|      FAST  |    1.025(R)|      SLOW  |   -0.018|    0.075|       -0.047|
CHC_N[6]          |    1.134(R)|      FAST  |    1.050(R)|      SLOW  |    0.016|    0.050|       -0.017|
CHC_P[0]          |    1.211(R)|      FAST  |    0.980(R)|      SLOW  |   -0.061|    0.120|       -0.091|
CHC_P[1]          |    1.153(R)|      FAST  |    1.035(R)|      SLOW  |   -0.003|    0.065|       -0.034|
CHC_P[2]          |    1.138(R)|      FAST  |    1.055(R)|      SLOW  |    0.012|    0.045|       -0.017|
CHC_P[3]          |    1.172(R)|      FAST  |    1.016(R)|      SLOW  |   -0.022|    0.084|       -0.053|
CHC_P[4]          |    1.182(R)|      FAST  |    1.010(R)|      SLOW  |   -0.032|    0.090|       -0.061|
CHC_P[5]          |    1.165(R)|      FAST  |    1.028(R)|      SLOW  |   -0.015|    0.072|       -0.043|
CHC_P[6]          |    1.131(R)|      FAST  |    1.053(R)|      SLOW  |    0.019|    0.047|       -0.014|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.214|         -  |       1.055|         -  |   -0.064|    0.045|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_c" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_CD_P"         "FALLING";
Worst Case Data Window 2.269; Ideal Clock Offset To Actual Clock 0.055;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process                      |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner           |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHC_N[0]          |   -2.119(F)|      FAST  |    4.310(F)|      SLOW  |   -0.064|    0.123|       -0.094|
CHC_N[1]          |   -2.177(F)|      FAST  |    4.365(F)|      SLOW  |   -0.006|    0.068|       -0.037|
CHC_N[2]          |   -2.192(F)|      FAST  |    4.385(F)|      SLOW  |    0.009|    0.048|       -0.020|
CHC_N[3]          |   -2.158(F)|      FAST  |    4.346(F)|      SLOW  |   -0.025|    0.087|       -0.056|
CHC_N[4]          |   -2.148(F)|      FAST  |    4.340(F)|      SLOW  |   -0.035|    0.093|       -0.064|
CHC_N[5]          |   -2.165(F)|      FAST  |    4.358(F)|      SLOW  |   -0.018|    0.075|       -0.047|
CHC_N[6]          |   -2.199(F)|      FAST  |    4.383(F)|      SLOW  |    0.016|    0.050|       -0.017|
CHC_P[0]          |   -2.122(F)|      FAST  |    4.313(F)|      SLOW  |   -0.061|    0.120|       -0.091|
CHC_P[1]          |   -2.180(F)|      FAST  |    4.368(F)|      SLOW  |   -0.003|    0.065|       -0.034|
CHC_P[2]          |   -2.195(F)|      FAST  |    4.388(F)|      SLOW  |    0.012|    0.045|       -0.017|
CHC_P[3]          |   -2.161(F)|      FAST  |    4.349(F)|      SLOW  |   -0.022|    0.084|       -0.053|
CHC_P[4]          |   -2.151(F)|      FAST  |    4.343(F)|      SLOW  |   -0.032|    0.090|       -0.061|
CHC_P[5]          |   -2.168(F)|      FAST  |    4.361(F)|      SLOW  |   -0.015|    0.072|       -0.043|
CHC_P[6]          |   -2.202(F)|      FAST  |    4.386(F)|      SLOW  |    0.019|    0.047|       -0.014|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.119|         -  |       4.388|         -  |   -0.064|    0.045|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_g" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_GH_P"         "RISING";
Worst Case Data Window 2.207; Ideal Clock Offset To Actual Clock 0.029;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process                      |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner            |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHG_N[0]          |    1.151(R)|      FAST  |    1.034(R)|      SLOW  |   -0.001|    0.066|       -0.034|
CHG_N[1]          |    1.143(R)|      FAST  |    1.045(R)|      SLOW  |    0.007|    0.055|       -0.024|
CHG_N[2]          |    1.146(R)|      FAST  |    1.039(R)|      SLOW  |    0.004|    0.061|       -0.029|
CHG_N[3]          |    1.151(R)|      FAST  |    1.034(R)|      SLOW  |   -0.001|    0.066|       -0.034|
CHG_N[4]          |    1.157(R)|      FAST  |    1.028(R)|      SLOW  |   -0.007|    0.072|       -0.040|
CHG_N[5]          |    1.141(R)|      FAST  |    1.047(R)|      SLOW  |    0.009|    0.053|       -0.022|
CHG_N[6]          |    1.146(R)|      FAST  |    1.042(R)|      SLOW  |    0.004|    0.058|       -0.027|
CHG_P[0]          |    1.148(R)|      FAST  |    1.037(R)|      SLOW  |    0.002|    0.063|       -0.031|
CHG_P[1]          |    1.140(R)|      FAST  |    1.048(R)|      SLOW  |    0.010|    0.052|       -0.021|
CHG_P[2]          |    1.143(R)|      FAST  |    1.042(R)|      SLOW  |    0.007|    0.058|       -0.026|
CHG_P[3]          |    1.148(R)|      FAST  |    1.037(R)|      SLOW  |    0.002|    0.063|       -0.031|
CHG_P[4]          |    1.154(R)|      FAST  |    1.031(R)|      SLOW  |   -0.004|    0.069|       -0.037|
CHG_P[5]          |    1.138(R)|      FAST  |    1.050(R)|      SLOW  |    0.012|    0.050|       -0.019|
CHG_P[6]          |    1.143(R)|      FAST  |    1.045(R)|      SLOW  |    0.007|    0.055|       -0.024|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.157|         -  |       1.050|         -  |   -0.007|    0.050|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_g" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_GH_P"         "FALLING";
Worst Case Data Window 2.207; Ideal Clock Offset To Actual Clock 0.029;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process                     |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner          |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHG_N[0]          |   -2.182(F)|      FAST  |    4.367(F)|      SLOW  |   -0.001|    0.066|       -0.034|
CHG_N[1]          |   -2.190(F)|      FAST  |    4.378(F)|      SLOW  |    0.007|    0.055|       -0.024|
CHG_N[2]          |   -2.187(F)|      FAST  |    4.372(F)|      SLOW  |    0.004|    0.061|       -0.029|
CHG_N[3]          |   -2.182(F)|      FAST  |    4.367(F)|      SLOW  |   -0.001|    0.066|       -0.034|
CHG_N[4]          |   -2.176(F)|      FAST  |    4.361(F)|      SLOW  |   -0.007|    0.072|       -0.040|
CHG_N[5]          |   -2.192(F)|      FAST  |    4.380(F)|      SLOW  |    0.009|    0.053|       -0.022|
CHG_N[6]          |   -2.187(F)|      FAST  |    4.375(F)|      SLOW  |    0.004|    0.058|       -0.027|
CHG_P[0]          |   -2.185(F)|      FAST  |    4.370(F)|      SLOW  |    0.002|    0.063|       -0.031|
CHG_P[1]          |   -2.193(F)|      FAST  |    4.381(F)|      SLOW  |    0.010|    0.052|       -0.021|
CHG_P[2]          |   -2.190(F)|      FAST  |    4.375(F)|      SLOW  |    0.007|    0.058|       -0.026|
CHG_P[3]          |   -2.185(F)|      FAST  |    4.370(F)|      SLOW  |    0.002|    0.063|       -0.031|
CHG_P[4]          |   -2.179(F)|      FAST  |    4.364(F)|      SLOW  |   -0.004|    0.069|       -0.037|
CHG_P[5]          |   -2.195(F)|      FAST  |    4.383(F)|      SLOW  |    0.012|    0.050|       -0.019|
CHG_P[6]          |   -2.190(F)|      FAST  |    4.378(F)|      SLOW  |    0.007|    0.055|       -0.024|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.176|         -  |       4.383|         -  |   -0.007|    0.050|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"         "RISING";
Worst Case Data Window 2.273; Ideal Clock Offset To Actual Clock 0.076;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process                      |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner           |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHA_N[0]          |    1.169(R)|      FAST  |    1.015(R)|      SLOW  |   -0.019|    0.085|       -0.052|
CHA_N[1]          |    1.174(R)|      FAST  |    1.010(R)|      SLOW  |   -0.024|    0.090|       -0.057|
CHA_N[2]          |    1.199(R)|      FAST  |    0.991(R)|      SLOW  |   -0.049|    0.109|       -0.079|
CHA_N[3]          |    1.151(R)|      FAST  |    1.033(R)|      SLOW  |   -0.001|    0.067|       -0.034|
CHA_N[4]          |    1.168(R)|      FAST  |    1.019(R)|      SLOW  |   -0.018|    0.081|       -0.050|
CHA_N[5]          |    1.237(R)|      FAST  |    0.954(R)|      SLOW  |   -0.087|    0.146|       -0.117|
CHA_N[6]          |    1.162(R)|      FAST  |    1.025(R)|      SLOW  |   -0.012|    0.075|       -0.043|
CHA_P[0]          |    1.166(R)|      FAST  |    1.018(R)|      SLOW  |   -0.016|    0.082|       -0.049|
CHA_P[1]          |    1.171(R)|      FAST  |    1.013(R)|      SLOW  |   -0.021|    0.087|       -0.054|
CHA_P[2]          |    1.196(R)|      FAST  |    0.994(R)|      SLOW  |   -0.046|    0.106|       -0.076|
CHA_P[3]          |    1.148(R)|      FAST  |    1.036(R)|      SLOW  |    0.002|    0.064|       -0.031|
CHA_P[4]          |    1.165(R)|      FAST  |    1.022(R)|      SLOW  |   -0.015|    0.078|       -0.047|
CHA_P[5]          |    1.234(R)|      FAST  |    0.957(R)|      SLOW  |   -0.084|    0.143|       -0.114|
CHA_P[6]          |    1.159(R)|      FAST  |    1.028(R)|      SLOW  |   -0.009|    0.072|       -0.040|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.237|         -  |       1.036|         -  |   -0.087|    0.064|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"         "FALLING";
Worst Case Data Window 2.273; Ideal Clock Offset To Actual Clock 0.076;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process                      |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner           |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHA_N[0]          |   -2.164(F)|      FAST  |    4.348(F)|      SLOW  |   -0.019|    0.085|       -0.052|
CHA_N[1]          |   -2.159(F)|      FAST  |    4.343(F)|      SLOW  |   -0.024|    0.090|       -0.057|
CHA_N[2]          |   -2.134(F)|      FAST  |    4.324(F)|      SLOW  |   -0.049|    0.109|       -0.079|
CHA_N[3]          |   -2.182(F)|      FAST  |    4.366(F)|      SLOW  |   -0.001|    0.067|       -0.034|
CHA_N[4]          |   -2.165(F)|      FAST  |    4.352(F)|      SLOW  |   -0.018|    0.081|       -0.050|
CHA_N[5]          |   -2.096(F)|      FAST  |    4.287(F)|      SLOW  |   -0.087|    0.146|       -0.117|
CHA_N[6]          |   -2.171(F)|      FAST  |    4.358(F)|      SLOW  |   -0.012|    0.075|       -0.043|
CHA_P[0]          |   -2.167(F)|      FAST  |    4.351(F)|      SLOW  |   -0.016|    0.082|       -0.049|
CHA_P[1]          |   -2.162(F)|      FAST  |    4.346(F)|      SLOW  |   -0.021|    0.087|       -0.054|
CHA_P[2]          |   -2.137(F)|      FAST  |    4.327(F)|      SLOW  |   -0.046|    0.106|       -0.076|
CHA_P[3]          |   -2.185(F)|      FAST  |    4.369(F)|      SLOW  |    0.002|    0.064|       -0.031|
CHA_P[4]          |   -2.168(F)|      FAST  |    4.355(F)|      SLOW  |   -0.015|    0.078|       -0.047|
CHA_P[5]          |   -2.099(F)|      FAST  |    4.290(F)|      SLOW  |   -0.084|    0.143|       -0.114|
CHA_P[6]          |   -2.174(F)|      FAST  |    4.361(F)|      SLOW  |   -0.009|    0.072|       -0.040|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.096|         -  |       4.369|         -  |   -0.087|    0.064|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

0 Kudos
Historian
Historian
4,594 Views
Registered: ‎01-23-2009

Re: Source Synchronous Input - OFFSET IN Hold Time violations

Jump to solution

Should I consider individual settings each data bit IDELAYE element.  That seems messy. 

 

While it is messy, it looks like this is a potential solution.

 

Of course, if I change my OFFSET IN constraints from 1.15ns/2.25ns to 1.25ns/2.35ns I get zero timing errors in all the paths. 

 

Yes, but if you increase it to 10ns/100ns it will also pass! But that isn't the timing of your interface! I presume the timing that you are using comes from your datasheet. If it is correct, then that is what you should use.

 

I will point out that there may be other things to consider that will hurt

  - is the JITTER on the input clock properly constrained (it goes with the PERIOD TIMESPEC)

     - you must specify the period, or cycle-cycle jitter - this is different (and much bigger) than the RMS jitter that may have been specified on the oscillator

     - the jitter will come from a combination of your oscillator jitter (fed to the ADC) and any jitter the ADC adds to the clock

  - is the duty cycle of the ADC clock guaranteed to be exactly 50/50

      - if not, then you need to derate your timing constraints to account for the difference

  - have you budgeted for the skew in your board routing from the ADC to the FPGA

 

All of these are small, but at these margins, they become important.

 

I have run two pieces of hardware using the timing shown below and have not seen any data errors over about 24 hours.

 

This is a good sign, but is hardly conclusive. This is 2 parts (out of the millions that Xilinx makes) at (presumably) lab temperature and two particular power supplies. To really be robust you must pass timing (ideally with some margin).

 

You should continue to  follow up with the experiments that I suggested. First, remove the IDELAY on the clock (that is currently set to 0). I don't know if this will make the margins better or worse (you will need to adjust your tap delays on the data to compensate for this, so you will have to run twice, one with data_tap=18, and one adjusted based on the results of the first one).

 

You should definitely try the other combinations

  - set both data and clock taps to 0 and see the sum of the margins. Again, this should be better by 180ps, which is a huge difference considering how close you are.

  - keep the clock IDELAY (and set it to 0) and remove the data IDELAY. See if this has a better sum of setup/hold margin than the other combinations

 

Again, lets worry about getting the best sum of setup+hold margin. Once we determine what that is, we can worry about fixing the timing constraints and choosing the tap values for the IDELAYs.

 

Avrum

Adventurer
Adventurer
4,584 Views
Registered: ‎06-30-2013

Re: Source Synchronous Input - OFFSET IN Hold Time violations

Jump to solution

HI Avrum:

 

I took your suggestion and looked at the sum of the setup and hold slack after I removed the IDELAYE for the clock (0 tap) It turned out that the sum gave me nearly a positive 600ps margin.  So I reduced the tap delay for the data from 18 to 13 and voila  I now have passing timing with almost 200ps for the setup time.  It looks like O could even do better by delaying the clock by fewer taps.

 

Thank you very much!  I never realized that removal of the clock path IDELAYE was a good option.

 

As for your other points, I do need to factor in the ADC clock duty cycle as it is 52/48 and not 50/50.  I did have a what I believe was a reasonable clock jitter spec on all thee ADC lane input clocks and I estimate clock to data routing skew to be less than 100ps.  Given this, I need to better account for these terms in my valid data window at the FPGA pins.

 

TIMEGRP "adc_data_c" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_CD_P"         "RISING";
Worst Case Data Window 1.593; Ideal Clock Offset To Actual Clock 0.199;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHC_N[0]          |    1.020(R)|      FAST  |    0.495(R)|      SLOW  |    0.130|    0.605|       -0.238|
CHC_N[1]          |    0.962(R)|      FAST  |    0.550(R)|      SLOW  |    0.188|    0.550|       -0.181|
CHC_N[2]          |    0.947(R)|      FAST  |    0.570(R)|      SLOW  |    0.203|    0.530|       -0.164|
CHC_N[3]          |    0.981(R)|      FAST  |    0.531(R)|      SLOW  |    0.169|    0.569|       -0.200|
CHC_N[4]          |    0.991(R)|      FAST  |    0.525(R)|      SLOW  |    0.159|    0.575|       -0.208|
CHC_N[5]          |    0.974(R)|      FAST  |    0.543(R)|      SLOW  |    0.176|    0.557|       -0.191|
CHC_N[6]          |    0.940(R)|      FAST  |    0.568(R)|      SLOW  |    0.210|    0.532|       -0.161|
CHC_P[0]          |    1.017(R)|      FAST  |    0.498(R)|      SLOW  |    0.133|    0.602|       -0.235|
CHC_P[1]          |    0.959(R)|      FAST  |    0.553(R)|      SLOW  |    0.191|    0.547|       -0.178|
CHC_P[2]          |    0.944(R)|      FAST  |    0.573(R)|      SLOW  |    0.206|    0.527|       -0.161|
CHC_P[3]          |    0.978(R)|      FAST  |    0.534(R)|      SLOW  |    0.172|    0.566|       -0.197|
CHC_P[4]          |    0.988(R)|      FAST  |    0.528(R)|      SLOW  |    0.162|    0.572|       -0.205|
CHC_P[5]          |    0.971(R)|      FAST  |    0.546(R)|      SLOW  |    0.179|    0.554|       -0.188|
CHC_P[6]          |    0.937(R)|      FAST  |    0.571(R)|      SLOW  |    0.213|    0.529|       -0.158|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.020|         -  |       0.573|         -  |    0.130|    0.527|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_c" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_CD_P"         "FALLING";
Worst Case Data Window 1.593; Ideal Clock Offset To Actual Clock 0.199;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHC_N[0]          |   -2.313(F)|      FAST  |    3.828(F)|      SLOW  |    0.130|    0.605|       -0.238|
CHC_N[1]          |   -2.371(F)|      FAST  |    3.883(F)|      SLOW  |    0.188|    0.550|       -0.181|
CHC_N[2]          |   -2.386(F)|      FAST  |    3.903(F)|      SLOW  |    0.203|    0.530|       -0.164|
CHC_N[3]          |   -2.352(F)|      FAST  |    3.864(F)|      SLOW  |    0.169|    0.569|       -0.200|
CHC_N[4]          |   -2.342(F)|      FAST  |    3.858(F)|      SLOW  |    0.159|    0.575|       -0.208|
CHC_N[5]          |   -2.359(F)|      FAST  |    3.876(F)|      SLOW  |    0.176|    0.557|       -0.191|
CHC_N[6]          |   -2.393(F)|      FAST  |    3.901(F)|      SLOW  |    0.210|    0.532|       -0.161|
CHC_P[0]          |   -2.316(F)|      FAST  |    3.831(F)|      SLOW  |    0.133|    0.602|       -0.235|
CHC_P[1]          |   -2.374(F)|      FAST  |    3.886(F)|      SLOW  |    0.191|    0.547|       -0.178|
CHC_P[2]          |   -2.389(F)|      FAST  |    3.906(F)|      SLOW  |    0.206|    0.527|       -0.161|
CHC_P[3]          |   -2.355(F)|      FAST  |    3.867(F)|      SLOW  |    0.172|    0.566|       -0.197|
CHC_P[4]          |   -2.345(F)|      FAST  |    3.861(F)|      SLOW  |    0.162|    0.572|       -0.205|
CHC_P[5]          |   -2.362(F)|      FAST  |    3.879(F)|      SLOW  |    0.179|    0.554|       -0.188|
CHC_P[6]          |   -2.396(F)|      FAST  |    3.904(F)|      SLOW  |    0.213|    0.529|       -0.158|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.313|         -  |       3.906|         -  |    0.130|    0.527|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_g" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_GH_P"         "RISING";
Worst Case Data Window 1.531; Ideal Clock Offset To Actual Clock 0.173;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHG_N[0]          |    0.957(R)|      FAST  |    0.552(R)|      SLOW  |    0.193|    0.548|       -0.178|
CHG_N[1]          |    0.949(R)|      FAST  |    0.563(R)|      SLOW  |    0.201|    0.537|       -0.168|
CHG_N[2]          |    0.952(R)|      FAST  |    0.557(R)|      SLOW  |    0.198|    0.543|       -0.173|
CHG_N[3]          |    0.957(R)|      FAST  |    0.552(R)|      SLOW  |    0.193|    0.548|       -0.178|
CHG_N[4]          |    0.963(R)|      FAST  |    0.546(R)|      SLOW  |    0.187|    0.554|       -0.184|
CHG_N[5]          |    0.947(R)|      FAST  |    0.565(R)|      SLOW  |    0.203|    0.535|       -0.166|
CHG_N[6]          |    0.952(R)|      FAST  |    0.560(R)|      SLOW  |    0.198|    0.540|       -0.171|
CHG_P[0]          |    0.954(R)|      FAST  |    0.555(R)|      SLOW  |    0.196|    0.545|       -0.175|
CHG_P[1]          |    0.946(R)|      FAST  |    0.566(R)|      SLOW  |    0.204|    0.534|       -0.165|
CHG_P[2]          |    0.949(R)|      FAST  |    0.560(R)|      SLOW  |    0.201|    0.540|       -0.170|
CHG_P[3]          |    0.954(R)|      FAST  |    0.555(R)|      SLOW  |    0.196|    0.545|       -0.175|
CHG_P[4]          |    0.960(R)|      FAST  |    0.549(R)|      SLOW  |    0.190|    0.551|       -0.181|
CHG_P[5]          |    0.944(R)|      FAST  |    0.568(R)|      SLOW  |    0.206|    0.532|       -0.163|
CHG_P[6]          |    0.949(R)|      FAST  |    0.563(R)|      SLOW  |    0.201|    0.537|       -0.168|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       0.963|         -  |       0.568|         -  |    0.187|    0.532|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_g" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_GH_P"         "FALLING";
Worst Case Data Window 1.531; Ideal Clock Offset To Actual Clock 0.173;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHG_N[0]          |   -2.376(F)|      FAST  |    3.885(F)|      SLOW  |    0.193|    0.548|       -0.178|
CHG_N[1]          |   -2.384(F)|      FAST  |    3.896(F)|      SLOW  |    0.201|    0.537|       -0.168|
CHG_N[2]          |   -2.381(F)|      FAST  |    3.890(F)|      SLOW  |    0.198|    0.543|       -0.173|
CHG_N[3]          |   -2.376(F)|      FAST  |    3.885(F)|      SLOW  |    0.193|    0.548|       -0.178|
CHG_N[4]          |   -2.370(F)|      FAST  |    3.879(F)|      SLOW  |    0.187|    0.554|       -0.184|
CHG_N[5]          |   -2.386(F)|      FAST  |    3.898(F)|      SLOW  |    0.203|    0.535|       -0.166|
CHG_N[6]          |   -2.381(F)|      FAST  |    3.893(F)|      SLOW  |    0.198|    0.540|       -0.171|
CHG_P[0]          |   -2.379(F)|      FAST  |    3.888(F)|      SLOW  |    0.196|    0.545|       -0.175|
CHG_P[1]          |   -2.387(F)|      FAST  |    3.899(F)|      SLOW  |    0.204|    0.534|       -0.165|
CHG_P[2]          |   -2.384(F)|      FAST  |    3.893(F)|      SLOW  |    0.201|    0.540|       -0.170|
CHG_P[3]          |   -2.379(F)|      FAST  |    3.888(F)|      SLOW  |    0.196|    0.545|       -0.175|
CHG_P[4]          |   -2.373(F)|      FAST  |    3.882(F)|      SLOW  |    0.190|    0.551|       -0.181|
CHG_P[5]          |   -2.389(F)|      FAST  |    3.901(F)|      SLOW  |    0.206|    0.532|       -0.163|
CHG_P[6]          |   -2.384(F)|      FAST  |    3.896(F)|      SLOW  |    0.201|    0.537|       -0.168|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.370|         -  |       3.901|         -  |    0.187|    0.532|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"         "RISING";
Worst Case Data Window 1.597; Ideal Clock Offset To Actual Clock 0.220;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHA_N[0]          |    0.975(R)|      FAST  |    0.533(R)|      SLOW  |    0.175|    0.567|       -0.196|
CHA_N[1]          |    0.980(R)|      FAST  |    0.528(R)|      SLOW  |    0.170|    0.572|       -0.201|
CHA_N[2]          |    1.005(R)|      FAST  |    0.509(R)|      SLOW  |    0.145|    0.591|       -0.223|
CHA_N[3]          |    0.957(R)|      FAST  |    0.551(R)|      SLOW  |    0.193|    0.549|       -0.178|
CHA_N[4]          |    0.974(R)|      FAST  |    0.537(R)|      SLOW  |    0.176|    0.563|       -0.193|
CHA_N[5]          |    1.043(R)|      FAST  |    0.472(R)|      SLOW  |    0.107|    0.628|       -0.261|
CHA_N[6]          |    0.968(R)|      FAST  |    0.543(R)|      SLOW  |    0.182|    0.557|       -0.188|
CHA_P[0]          |    0.972(R)|      FAST  |    0.536(R)|      SLOW  |    0.178|    0.564|       -0.193|
CHA_P[1]          |    0.977(R)|      FAST  |    0.531(R)|      SLOW  |    0.173|    0.569|       -0.198|
CHA_P[2]          |    1.002(R)|      FAST  |    0.512(R)|      SLOW  |    0.148|    0.588|       -0.220|
CHA_P[3]          |    0.954(R)|      FAST  |    0.554(R)|      SLOW  |    0.196|    0.546|       -0.175|
CHA_P[4]          |    0.971(R)|      FAST  |    0.540(R)|      SLOW  |    0.179|    0.560|       -0.191|
CHA_P[5]          |    1.040(R)|      FAST  |    0.475(R)|      SLOW  |    0.110|    0.625|       -0.258|
CHA_P[6]          |    0.965(R)|      FAST  |    0.546(R)|      SLOW  |    0.185|    0.554|       -0.185|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       1.043|         -  |       0.554|         -  |    0.107|    0.546|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

TIMEGRP "adc_data_a" OFFSET = IN 1.15 ns VALID 2.25 ns BEFORE COMP "CLK_AB_P"         "FALLING";
Worst Case Data Window 1.597; Ideal Clock Offset To Actual Clock 0.220;
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
CHA_N[0]          |   -2.358(F)|      FAST  |    3.866(F)|      SLOW  |    0.175|    0.567|       -0.196|
CHA_N[1]          |   -2.353(F)|      FAST  |    3.861(F)|      SLOW  |    0.170|    0.572|       -0.201|
CHA_N[2]          |   -2.328(F)|      FAST  |    3.842(F)|      SLOW  |    0.145|    0.591|       -0.223|
CHA_N[3]          |   -2.376(F)|      FAST  |    3.884(F)|      SLOW  |    0.193|    0.549|       -0.178|
CHA_N[4]          |   -2.359(F)|      FAST  |    3.870(F)|      SLOW  |    0.176|    0.563|       -0.193|
CHA_N[5]          |   -2.290(F)|      FAST  |    3.805(F)|      SLOW  |    0.107|    0.628|       -0.261|
CHA_N[6]          |   -2.365(F)|      FAST  |    3.876(F)|      SLOW  |    0.182|    0.557|       -0.188|
CHA_P[0]          |   -2.361(F)|      FAST  |    3.869(F)|      SLOW  |    0.178|    0.564|       -0.193|
CHA_P[1]          |   -2.356(F)|      FAST  |    3.864(F)|      SLOW  |    0.173|    0.569|       -0.198|
CHA_P[2]          |   -2.331(F)|      FAST  |    3.845(F)|      SLOW  |    0.148|    0.588|       -0.220|
CHA_P[3]          |   -2.379(F)|      FAST  |    3.887(F)|      SLOW  |    0.196|    0.546|       -0.175|
CHA_P[4]          |   -2.362(F)|      FAST  |    3.873(F)|      SLOW  |    0.179|    0.560|       -0.191|
CHA_P[5]          |   -2.293(F)|      FAST  |    3.808(F)|      SLOW  |    0.110|    0.625|       -0.258|
CHA_P[6]          |   -2.368(F)|      FAST  |    3.879(F)|      SLOW  |    0.185|    0.554|       -0.185|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|      -2.290|         -  |       3.887|         -  |    0.107|    0.546|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

Adventurer
Adventurer
7,910 Views
Registered: ‎06-30-2013

Re: Source Synchronous Input - OFFSET IN Hold Time violations

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Hi Avrum:

 

After performing the experimentation you suggested and tightening my constraints to account for the 52$ clock duty cycle and reducing my valid window time and OFFSET IN time to account for 50ps of routing skew, I was able to achieve almost 400 ps of positive slack on both set-up and hold times for all paths.  This was done with no clock IDELAYE, a BUFR on the clock path to the IDDR clock input and a reduction in the data path IDELAYE to 10 taps.

 

With your guidance my understanding of the fabric and the methodology to achieve timing closure is much improved.

 

I now believe my design is robust enough to handle device PVT and supply variations and will begin testing in the lab

 

Thank you for your support!

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